12 LVPECL/24 CMOS Output Clock
Generator with Integrated 1.6 GHz VCO
AD9520-4 Rev. 0
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responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights rerved.
FEATURES
Low pha noi, pha-locked loop (PLL)
On-chip VCO tunes from 1.4 GHz to 1.8 GHz
Supports external 0 V to 5 V VCO/VCXO to 2.4 GHz
1 differential or
2 single-ended reference inputs
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Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.67 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes,
with lectable revertive/nonrevertive switching Glitch-free switchover between references
Automatic recover from holdover
Digital or analog lock detect, lectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 4 has a 1-to-32 divider with pha delay Additive output jitter as low as 225 f S rms
Channel-to-channel skew grouped outputs <16 ps
Each LVPECL output can be configured as two CMOS
outputs (for f OUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed
SPI- and I²C-compatible rial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration ttings APPLICATIONS
Low jitter, low pha noi clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-41 provides a multioutput clock distribution function with subpicocond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to 1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be ud.
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Figure 1.
The AD9520 rial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the rial interface and store ur-defined register tting for power-up and chip ret.
The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and pha (coar delay) to be t.
The AD9520 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. A parate output driver power supply can be from 2.375 V to 3.465 V.
The AD9520 is specified for operation over the standard industrial range of −40°C to +85°C.
loveless1 The AD9520 is ud throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-4 is ud, it is referring to that specific member of the AD9520 family.
AD9520-4
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TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics .........................................
....................... 8 Timing Diagrams ..................................................................... 9 Clock Output Additive Pha Noi (Distribution Only; VCO Divider Not Ud) ...................................................................... 10 Clock Output Absolute Pha Noi (Internal VCO Ud) .. 11 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ............................................................................. 11 Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO) ............................................................................. 11 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 12 Clock Output Additive Time Jitter (VCO Divider Not Ud)....................................................................................................... 12 Clock Output Additive Time Jitter (VCO Divider Ud) ..... 13 Serial Control Port—SPI Mode ................................................ 13 Serial Control Port—I2C Mode ................................................ 14 PD , SYNC , and RESET Pins ..................................................... 15 Serial Port Setup Pins: SP1, SP0 ............................................... 15 LD, STATUS, 15 Power Dissipation ....................................................................... 16 Absolute Maximum Ratings .......................................................... 17 Thermal Resistance .................................................................... 17 ESD Caution ................................................................................ 17 Pin Configuration and Function Descriptions ....
....................... 18 Typical Performance Characteristics ........................................... 21 Terminology .................................................................................... 26 Detailed Block Diagram ................................................................ 27 Theory of Operation ...................................................................... 28 Operational Configurations ...................................................... 28 Mode 0: Internal VCO and Clock Distribution .. (28)
Mode 1: Clock Distribution or External
VCO <1600 MHz ................................................................... 30 Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz .................................................. 32 Pha-Locked Loop (PLL) .................................................... 34 Configuration of the PLL ...................................................... 34 Pha Frequency Detector (PFD) ........................................ 34 Charge Pump (CP) ................................................................. 35 On-Chip VCO ........................................................................ 35 PLL External Loop Filter ....................................................... 35 PLL Reference Inputs ............................................................. 35 Reference Switchover ............................................................. 36 Reference Divider R ...................
............................................ 36 VCXO/VCO Feedback Divider N: P , A, B, R ..................... 36 Digital Lock Detect (DLD) ................................................... 38 Analog Lock Detect (ALD) ................................................... 38 Current Source Digital Lock Detect (CSDLD) .................. 38 External VCXO/VCO Clock Input (CLK/CLK ) ................ 39 Holdover .................................................................................. 39 Manual Holdover Mode ........................................................ 39 Automatic/Internal Holdover Mode .................................... 39 Frequency Status Monitors ................................................... 41 VCO Calibration .................................................................... 42 Zero Delay Operation ................................................................ 43 Internal Zero Delay Mode ..................................................... 43 External Zero Delay Mode .................................................... 43 Clock Distribution ..................................................................... 44 Operation Modes ................................................................... 44 CLK or VCO Direct-to-LVPECL Outputs .......................... 44 Clock Frequency Division ..................................................... 45 VCO Divider ........................................................................... 45 Channel Dividers ................................................................... 45 Synchronizing the Outputs—SYNC Function ................... 47 LVPECL Output Drivers ....................................................... 48 CMOS Output Drivers .......................................................... 49 Ret Modes ...........................................................................
..... 49 Power-On Ret ...................................................................... 49 Hardware Ret via the RESET Pin ..................................... 49 Soft Ret via the Serial Port ................................................. 49 Soft Ret to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port . (49)
AD9520-4
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Power-Down Modes (49)
Chip Power-Down via PD ..................................................... 49 PLL Power-Down .................................................................... 50 Distribution Power-Down ..................................................... 50 Individual Clock Output Power-Down ................................ 50 Individual Clock Channel Power-Down .. (50)
Serial Control Port .......................................................................... 51 SPI/I2C Port Selection ................................................................ 51 I2C Serial Port Operation ........................................................... 51 I 2C Bus Characteristics ........................................................... 51 Data Transfer Process ...........................................................
.. 52 Data Transfer Format ............................................................. 53 I2C Serial Port Timing ............................................................ 53 SPI Serial Port Operation ........................................................... 54 Pin Descriptions ...................................................................... 54 SPI Mode Operation ............................................................... 54 Communication Cycle—Instruction Plus Data .................. 54 Write ......................................................................................... 54 Read .......................................................................................... 54 SPI Instruction Word (16 Bits) .................................................. 55 SPI MSB/LSB First Transfers ..................................................... 55 EEPROM Operations ..................................................................... 58 Writing to the EEPROM ............................................................ 58 Reading from the EEPROM ...................................................... 58 Programming the EEPROM 59 Register Section Definition Group ....................................... 59 IO_UPDATE (Operational Code 0x80) .............................. 59 End-of-Data (Operational Code 0xFF) ............................... 59 Pudo-End-of-Data (Operational Code 0xFE) ................. 59 Thermal Performance ..................................................................... 61 Register Map .................................................................................... 62 Register Map Descriptions ............................................................. 67 Applications Information .......................................................
........ 82 Frequency Planning Using the AD9520 .................................. 82 Using the AD9520 Outputs for ADC Clock Applications .... 82 LVPECL Clock Distribution ...................................................... 82 CMOS Clock Distribution ......................................................... 83 Outline Dimensions ........................................................................ 84 Ordering Guide (84)
REVISION HISTORY
9/08—Revision 0: Initial Version没什么大不了的英文
AD9520-4
SPECIFICATIONS
Typical (typ) is given for VS = VS_DRV = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; T A = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwi noted. Minimum (min) and maximum (max) values are given over full VS and T A (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
VS 3.135 3.3 3.465 V 3.3 V ± 5%
VS_DRV 2.375 VS V This is nominally 2.5 V to 3.3 V ± 5%
netsVCP VS 5.25 V This is nominally 3.3 V to 5.0 V ± 5%
RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground
CPRSET Pin Resistor 5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual
current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
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AD9520-4
cyber mondayRev. 0 | Page 5 of 84科室牌翻译
Parameter Min Typ Max Unit Test Conditions/Comments Crystal Oscillator Crystal Resonator Frequency Range 16.67 33.33 MHz Maximum Crystal Motional Resistance 30 Ω PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pul width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pul width = 6.0 ns Reference Input Clock Doubler Frequency 0.004 50 MHz Antibacklash pul width = 1.3 ns, 2.9 ns Antibacklash Pul Width 1.3 ns 0x017[1:0] = 01b 2.9 ns 0x017[1:0] = 00b; 0x017[1:0] = 11b 6.0 ns 0x017[1:0] = 10b CHARGE PUMP (CP) I CP Sink/Source Programmable High Value 4.8 mA With CPRSET = 5.1 kΩ; higher I CP is possible by
changing CPRSET
Low Value 0.60 mA With CPRSET = 5.1 kΩ; lower I CP is possible by
changing CPRSET
Absolute Accuracy 2.5 % Charge pump voltage t to V CP /2 CPRSET Range 2.7 10 kΩ I CP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 1 % 0.5 < V CP < VCP − 0.5 V; V CP is the voltage on the CP (charge
pump) pin; VCP is the voltage on the VCP power supply pinbeudfor
I CP vs. V CP 1.5 % 0.5 < V CP < VCP − 0.5 V I CP vs. Temperature 2 % V CP = VCP/2 V PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input
po什么意思
frequency divided by P)
PLL N DIVIDER DELAY Register 0x019[2:0]; e Table 53000 Off 001 410 ps 010 530 ps 011 650 ps 100 770 ps 101 890 ps 110 1010 ps 111 1130 ps PLL R DIVIDER DELAY Register 0x019[5:3]; e Table 53000 Off 001 370 ps 010 490 ps 011 610 ps 100 730 ps 101 850 ps 110 970 ps 111 1090 ps
AD9520-4
1 The REFIN and REFIN lf-bias points are offt slightly to avoid chatter on an open input condition.
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
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