in Figure 2 are detected during test and scan mode.
7: Testing delay faults
genos
There is another class of faults in micropipelines which can be detected using the propod scan test technique.The are delay faults in combinational circuits between the stage registers of the micropipeline. The output data of each combinational logic block is latched after a certain delay when the data has arrived at its inputs. A delay fault in this combinational block will extend path delays. In the prence of such a fault the bundled data interface of the correspondent micropipeline stage will be violated, i.e. the outputs of the combinational logic will be latched before the output signals in the bundle are stable.
The algorithm ud to detect delay faults in the process-ing logic of the micropipeline is similar to that exploited in delay testing of synchronous circuits which has been adapted by Khoche and Brunvand [12]. Basically, the pair of test patterns ( and ) must be applied to the inputs of the combinational circuit to detect its path delay faults.According to this test approach three stage registers (, and ) are ud to detect delay faults in the combi-national logic . The tests and are stored in the reg-isters and respectively. The results of the test are saved in the register . When the test patterns are loaded into th
e stage registers the combinational circuit is ttled (test ). The delay fault is tested by applying a request signal to the input Rin of the micropipeline t in normal operation mode. This caus the application of the test to the inputs of the logic (=()). A data path of the circuit under test is activated. If there is a delay fault in this path it will cau a delayed respon by the combinational circuit whereas the respons are latched after a fixed time determined by the corresponding delay.
8: Conclusions
The scan test technique prented in this paper supports testing for stuck-at and delay faults in micropipelines. The internal inputs and outputs of the processing logic blocks are fully controllable and obrvable through the scan path.The test patterns are scanned into the registers and the test results are shifted out from the register latches, united into one shift register. The scan path of the testable micropipe-line is controlled by the STCL block. Two implementations of the STCL blocks which follow two different communi-cation protocols have been prented. The universal struc-tures of the STCL blocks allow them to be adapted for arranging either a global asynchronous shifting of the test data between different parts of the chip or a local scan path within a particular block.
The propod testable micropipeline structure greatly
p 1p 2R i 1–R i R i 1+F i p 3p 1R i 1–R i R i 1+p 1p 2F i p 2F i 1–p 3simplifies the testing of micropipelines reducing the test complexity to that of the processing logic. The overall overhead can be estimated only for a particular ca since it depends on the complexity of the processing logic.
Acknowledgements
The authors would like to express their gratitude to the members of the AMULET rearch group for creating the stimulating environment for this work.
References
家人的英文
[1]
C. L. Seitz, “System timing,” Chapter 7, in Introduction to VLSI Systems , C. Mead and L. Conway, Addison-Wesley,1980.
[2]
G. Gopalakrishnan, P. Jain, “Some recent asynchronous system design methodologies,”Technical Report UU-CS-TR-90-016, University of Utah, Oct. 1990.
buyer
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L. Lavagno, A. Sangiovanni-Vincentelli, “Algorithms for synthesis and testing of asynchronous circuits,” Kluwer Academic Publishers, 1993.
[4]
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, J. V .Woods, “AMULET1: A micropipelined ARM,”Proc.IEEE Comput. Conf., March 1994.
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G. Rusll, I. L. Sayers, “Advanced simulation and test methodologies for VLSI design,” Van Nostrand Reinhold (International), 1989.
[6]
Chin-Long Wey, Ming-Der Shieh, D. Fisher, “ASCLScan:a scan design for asynchronous quential circuits,” in Pro-ceedings of the IEEE Int. Conf. on Computer-Aided Design , pp. 159-162, 1993.
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P. Thorel, J. L. Rainard, A. Botta, A. Chemarin, J. Majos,“Implementing boundary-scan and pudo-random BIST in an asynchronous transfer mode switch,” Int. Test Conf.,1991, pp. 131-139.
[8]
M. Roncken, “Partial scan test for asynchronous circuits illustrated on a DCC error corrector,” in Proc. Int. Sympo-sium on Advanced Rearch in Asynchronous Circuits and Systems (Async94), Nov. 1994.
[9]I. E. Sutherland, “Micropipelines,”Communications of the ACM , V ol. 32, no. 6, pp. 720-738, June 1989.
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P. Day and J. Viv. Woods, “Investigation into Micropipe-line Latch Design Styles,”to be published in IEEE Trans.VLSI circuits , June 1995.
[11]
S. Pagey, G. Venkatesh, S. Sherlekar, “Issues in fault mod-elling and testing of micropipelines,”First Asian Test Sym-posium , Hiroshima, Japan, Nov. 1992.
[12]
A. Khoche, E. Brunvand, “Testing micropipelines,” in Proc. Int. Symposium on Advanced Rearch in Asynchro-nous Circuits and Systems (Async94), Utah, Nov. 1994.[13]
O. Petlin, S. Furber, “Scan testing of asynchronous quen-tial circuits,” in Proc. 5th Great Lakes Symposium on VLSI ,New York, March 1995.
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P. A. Beerel, T. H.-Y . Meng, “Semi-modularity and lf-diagnostic asynchronous control circuits,”Proceedings of the Conf. on Advanced Rearch in VLSI / editor Carlo H.Sequin,MIT Press, Santa Cruz, March 1991, pp. 103-117.
goes high and a rising event is generated on the request out-put RSout . If nASout =RSin =0 the C-element is t to zero.Thus, the signal Sc is ret to zero, rising and falling events are produced on the control lines nASin and RSout respec-tively. The delays of the control signals in the STCL block are prented in Table III. The results show that the u of the 4-pha STCL block improves the performance of the shift operation.
6: Test strategy
The strategy we propo for testing stuck-at faults in micropipelines is very similar to that ud in scan testing synchronous circuits. If Sc =0 the micropipeline shown in Figure 4 can perform in normal operation mode (Tst=0) or in test mode (Tst=1). In scan mode (Tst =0,De =0), the test patterns are loaded into the stage registers which are con-figured as a united scan register. The scan path is created by connecting the inputs Sin in ries to the outputs Sout of all the stage registers. Clock signals Sc for controlling the shift operation are generated internally by the STCL. When the test patterns are loaded into the latches the micropipeline is t to test mode (Tst =1). A request signal is produced on the line Rin of the micropipeline. The respons from each processing block are stored in the registers. When Tst =0 the contents of the latches are shifted to the output Sout of the last stage register. The test results are compared with known good ones. Whilst shifting out the test results to the output Sout a new test pattern is loaded from the input Sin .The test procedure is repeated. Thus, the complexity of
TABLE III:
4-pha scan test control delays
testing the micropipeline is reduced to the testing of its processing logic which compris mostly combinational circuits.
6.1: Testing for faults in the STCL
The STCL unit of the testable micropipeline is an addi-tional control block which is not ud in norma
l operation mode. Nevertheless, it must be fault free as it controls the scan path of the micropipeline. A stuck-at fault on any of the lines in the STCL block prevents the generation of the control signals on its outputs. This is becau the STCL is a fully delay-innsitive asynchronous circuit where every control signal handshakes with others. Such circuits are fully testable for stuck-at faults [14].
6.2: Testing for faults in the control logic
llosaAs was mentioned earlier, stuck-at faults on the control lines of the micropipeline can be detected easily since they cau the micropipeline to halt. This happens becau a micropipeline is an event-driven asynchronous circuit [9].Such stuck-at faults can be identified either in normal oper-ation mode or during the test.
6.3: Testing for faults in the processing logic思路中文
It is assumed that all the processing blocks between the stages of the micropipeline are combinational circuits. The internal inputs of each combinational circuit are controlla-ble and its outputs are obrvable through the scan path of the micropipeline. Tests for detecting stuck-at faults in all the processing blocks can be derived using well known test generation algorithms such as the D-algorithm, PODEM,FAN and others [5].
6.4: Testing for faults in the latches
Two types of stuck-at faults are considered for the reg-ister latches: stuck-at-capture and stuck-at-pass faults.Stuck-at-capture (stuck-at-pass) faults of the scan latch (e Figure 2) can be caud by stuck-at faults on the con-trol lines of the tristate buffers and inverters which disable (enable) them permanently. Most of the faults can be detected by shifting an alternating 0-1 test through the latches united in one scan register. A stuck-at-1 fault on the input nTst of the latch can be identified during test mode when the faulty scan latch and its predecessor are t to dif-ferent states. In this ca the state of the faulty latch will be changed. Stuck-at-0 and stuck-at-1 faults on the line De of are detected by driving the input Din with a different logic value to its current state during test mode and scan mode respectively.
Stuck-at faults on the data lines of the scan latch shown
L 1L 1L 2
Test mode . During the test (Tst =1,Sc =0) the test vectors are stored in the first latches . The outputs of the latches are connected through the multiplexers to the out-puts of the stage register. After receiving a request signal on the line Rq the data is stored into the latches of the reg-ister (e Figu
re 3). The test vectors and the test results are saved in different latches becau the data flows through the micropipeline from left to right while the test vectors must be prerved during the test.
5: Scan test control
The testable micropipeline design is shown in Figure 4.It compris a micropipeline and the scan test control logic (STCL) unit. The stage registers of such a micropipeline are built using scan latches. The STCL block is ud to make an asynchronous test interface for the micropipeline.
L 1L 2
described allows the detection of all the stuck-at faults and bundling constraint violations in micropipelines. However,this scan test technique has been developed only for micro-pipelines which u a two-pha transition signalling pro-tocol. The scan test interface us clocks produced by a clock generator which is not always available in asynchro-nous VLSI designs.
A method to design and test asynchronous quential circuits bad on the micropipeline design style has been reported [13]. The test approach is implemented using spe-cially designed scan latches manipulated by the scan test control logic. In this paper, we extend this test method to the testing of general micropipeline structures.
4: Scan test design
4.1: Scan latch implementation
Figure 2 shows a CMOS implementation of the scan latch structure which contains two latches ( and ) and a multiplexer.
In normal operation mode (the test control signal Tst is low) the tristate inverter of is clod since the shift clock signal Sc is held at zero (nSc =1). When the data enable sig-nal (De ) is high the input data (Din ) pass to the output Dout and is latched by when De is low.
In scan mode (Tst =0,nTst =1) the enable signal De is low so that the tristate buffer of is clod. When the clock signal Sc is high (nSc =0) the scan data from the scan-in input (Sin ) is latched by the latch and pass to the tristate inverter of . While Sc =1, is opened and the shift data is nt to the scan-out output (Sout ) of the scan latch. When Sc =0 (nSc =1) the scan data bit is latched by and the latch is opened. This procedure is similar to that ud for storing the data in a master-slave flip-flop.
L 1L 2L 2L 2L 2L 1L 2L 2L 2L 1
triumphs
data comes to the micropipeline from outside and is trans-ferred through the stage registers. If there are no processing blocks (usually combinational circuits) between stages the micropipeline performs as an ordinary first-in first-out (FIFO) buffer. The data processing procedure is controlled by C-elements which are state-holding ‘rendezvous’ ele-ments performing the AND function for events.
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Initially, all the C-elements are t to zero. When the data is ready on the inputs Din of the micropipeline the nder issues a request on the line Rin . The first C-element transfers a request signal to the first register (Reg1) which latches the data and generates an acknowledge (Ain ) to the nder. A signal Ack from Reg1 is delayed for the time required to complete the data processing performed by the combinational logic (CL1). When the data is stable on the outputs of CL1 the cond C-element nds a request to the next stage register (Reg2). As a conquence, the data is latched in Reg2 and the first C-element is primed by an acknowledge signal generated by Reg2. New data can be written into Reg1 and the process of transferring the data through the subquent stages of the micropipeline is repeated. When the data reaches the last stage of the micro-pipeline a request (Rout ) is produced for the receiver which completes the handshaking protocol by nding an acknowledge on the line Aout .
right round
Every micropipeline stage works in parallel and nds the data to the neighbour stage only when the
data is ready to be procesd. The data is latched in registers. There are different ways to implement the control of latching and storing the data in the latches of the micropipeline registers.Basically, the latches are controlled by a pair of control sig-nals such as ‘pass’ and ‘capture’ [9]. In the initial state all the register latches can be either transparent or in the cap-ture mode depending on the latch transition controlling protocol. The u of ‘normally clod’ latches is preferable from the power consumption point of view since no transi-tions in the data paths can occur unless new data has been latched by the stage register [10].
3: Testing micropipelines
3.1: Faults in micropipelines
There are a few works devoted to fault modelling and fault testing problems in micropipelines [11-13]. Stuck-at faults in the control part, combinational logic blocks and latches of the micropipeline have been considered [11].Faults in the control part
The are faults on the inputs and outputs of the C-ele-ments and the request and acknowledge lines of the micro-pipeline. As was shown the micropipeline moves through at most one step and then halts in the prence of a stuck-at fault in its control part. Thus, such stuck-at faults can be identified easily during normal operation mode.Faults in the processing logic
It was assumed that all the latches of the micropipeline are transparent initially. This allows the processing logic to be treated as a single combinational circuit. To detect any of the single stuck-at faults in such a circuit test vectors can be obtained using any known test generation techniques [5].
Faults in the latches
It was considered that a stuck-at fault inside the latch can put it permanently in capture (stuck-at-capture fault) or pass (stuck-at-pass fault) mode. Any stuck-at fault on the inputs or outputs of the stage register or stuck-at-capture fault of the transition latch is equivalent to the correspond-ent stuck-at fault in the combinational logic block. To detect a stuck-at-pass fault in the transition latch tw谷歌在线翻译
o test patterns are required.
3.2: Scan testing
An elegant scan test approach has been propod by Khoche and Brunvand [12]. The micropipeline can work in two modes: normal operation and scan test mode. The micropipeline performs to its specification in normal oper-ation mode. In test mode, all the latches are configured into one shift register where each latch works as an ordinary master-slave flip-flop. The stage registers of the micropipe-line are clocked through the control lines where the input Aout is ud as a clock input. The C-elements pass their negated inputs onto the outputs forming a clocking line for the scan path. As a result, the test patterns are loaded from the scan-in input into all the latches of the micropipeline.Afterwards the micropipeline is returned to normal opera-tion mode in which only one request signal is generated. To obrve the contents of the register latches the micropipe-line is t to scan test mode. The contents of all the latches are shifted out to the scan-out output. The test technique
Scan Testing of Micropipelines
O. A. Petlin, S. B. Furber Department of Computer Science, The University, Oxford Road, Manchest
er, M13 9PL, U.K.
Abstract
The micropipeline approach to designing asynchronous VLSI circuits has successfully been ud in the AMULET1 microprocessor. A method to design and test micropipe-lines is prented in this paper. The test strategy is bad on the scan test technique. It allows the parate testing of all the data processing blocks by scanning the test patterns in and shifting the respons out of the stage registers. The propod test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.
1: Introduction
Asynchronous VLSI designs may have advantages over their synchronous counterparts. The clock skew problem no longer exists in asynchronous circuits since they do not u global clocks. In addition, asynchronous circuits have a potential for lower power consumption [1-3].
An asynchronous version of the ARM6 microprocessor (AMULET1) has been designed by the AMUL
ET rearch group at the Department of Computer Science in the Uni-versity of Manchester and fabricated by GEC Plesy Sem-iconductors Limited. AMULET1 was designed using the micropipeline design approach which offers a good engi-neering framework for the design of complex asynchro-nous VLSI circuits [4].
The design process for asynchronous circuits must take into account all hazards and races to ensure a proper signal-ling interface. From this point of view the testing of circuits without synchronization clocks is complex [3]. As a result, testing asynchronous VLSI designs prents new problems which must be addresd before their commercial potential can be realized. The most widely ud fault models chon to describe fault behaviours of asynchronous circuits are stuck-at and delay (transition) faults [3,5]. The scan test technique has been adapted well to the testing of asynchro-nous circuits [6-8]. Unfortunately, the results have been obtained for specific asynchronous designs and cannot be ud for the testing of micropipelines.
2: Micropipelines
Micropipelines were introduced by Ivan Sutherland in his Turing Award lecture [9]. Micropipelines are asynchro-nous, event-driven pipelines bad on the ‘bundled data’interface. In micropipelines, the d中英文在线翻译器
ata is treated as a bundle, i.e. when the data produced by the nder is ready (the data outputs are stable) the nder issues a ‘request’ event to the receiver; the receiver acknowledges the receipt of the data by nding an ‘acknowledge’ event. This handshaking mechanism is repeated when further data is produced by the nder.
2.1: Transition signalling
The data transfer protocol in micropipelines is control-led by ‘transition’ signals. There are two types of signalling protocols ud in asynchronous circuits: 2-pha and 4-pha signalling protocols. According to the 2-pha tran-sition signalling protocol both rising and falling transition events have the same meaning. When the data is ready to be nt to the receiver the nder produces a rising (or fall-ing) request signal which is acknowledged by a rising (or falling) signal on the acknowledge control line. 4-pha signalling differs from the 2-pha protocol in that both the control signals (request and acknowledge) must be returned to zero, i.e. new data can be transmitted only when both control signals are zero.
2.2: Micropipeline structures
Figure 1 illustrates a micropipeline with four stages. The
