Allegro® Design Entry HDL Reu Tutorial
Product Version 16.3 April 2010
A
Frequently Asked Questions
This FAQ has answers to the following questions:
What is the difference between creating a hierarchical design and
implementing design reu?
Can I have a subdesign as a standalone design?
How do I control reference designators in subdesigns?
In which situations should I u the GEN_SUBDESIGN, FORCE_SUBDESIGN, and USE_SUBDESIGN directives?
What happens if I do not specify the subdesign name in the
FORCE_SUBDESIGN or USE_SUBDESIGN directive while packaging the top-level design?
Can I reu a design that includes instances of other designs?
How do I add properties in the top-level design and force them to appear in one or multiple sub-level design blocks?
I have a design in PSD 13.6 and implemented design reu. How do I migrate
the design to PSD 14.2?
What is the change in the Design Reu flow in PSD 13.6 and PSD 14.0?
Can I edit properties in a reusable block while using it in my design?
Can I have nested reu modules? What precautions must I follow to manage nested reu modules?
How can I u modules in PCB Editor that are not associated with a schematic?
How can I import or export subdrawings from within PCB Editor?
Can I leverage unud gates in a module?
If I make changes in PCB Editor to a part or parts from a reud module and I feedback the changes to the Design Entry HDL schematic, do I need to add
any reu-specific directives while packaging?
If I u a block in a design then do I have to exerci any precaution while
naming logical libraries?
How do I specify a temp location for the library containing a read-only block? What is the difference between creating a hierarchical design and implementing design reu?
Overview of Hierarchical Design
When you create a software application, theoretically, it is possible that you can u a single file to create the application. However, maintenance will turn costly and painful. You u subroutines and functions to break the complexity of the software application, and save the code in different logically connected files to allow for easier maintenance and troubleshooting. Similar to creating a software a
pplication in one large file is the process of creating a flat schematic. You can have your complete design in a single flat schematic. However, you can u a hierarchical design to divide the complexity of a design into logical subts or blocks. This will allow for easier maintenance and distribution of work within the design team.
In a hierarchical design, you create blocks to embed a logical design within another design. Each block is promoted once in the design but is ud multiple times in the schematic.
Advantages of Hierarchical Design
The u of hierarchical design makes the top-level data flow easy to read. Becau you do not need to manually add components each time you u a block, the design remains compact. You can replicate the blocks, and debug and simulate them. If you need to make changes to a component in a block, you can update the block and re-initialize each instance of that block.
Limitations of Hierarchical Design and the Need for Design Reu
You may require to reu the blocks created for one design in another design. In such cas, if you u hierarchical blocks, you will be able to reu them only in the schematic. However if you do desi
gn reu, you would be able to u the blocks both in the schematic and on the board, that is, across the PCB front-to-back flow. Further, the design reu block rves as a ready-made PCB board that does not require any placement and routing.
Unlike blocks in a hierarchical design, the modules in reud designs contain the schematic design, the physical netlist (packaging information), and the physical board placement and routing information. This adds the edge to reusability. After you have saved modules in a library, you can view and reu them in any future design.
Modules can be updated if the master module is changed (similar to the way in which library components are refreshed). Components within modules can also be
updated if tho components have changed in the library.
In summary, creating a hierarchical design is a best practice for design creation, which increas productivity and reus effort for a particular design. Design reu is, however, an organization-level activity where you reu your existing intellectual property (IP).
Note: This tutorial covers the procedure for creating a reusable logical and physical module. To reus
e the modules effectively, you need an IP management system that manages the metatags required to access the individual modules in different designs. Using such an IP management system is outside the scope of the tutorial. Can I have a subdesign as a standalone design?
Yes, you can have a subdesign as a standalone design. A subdesign is a complete design in itlf. It has the same property and connectivity information as a standalone design and some additional reu properties that provide the necessary
information whenever the subdesign is reud in a larger design.
Therefore, it is possible to have a subdesign as a standalone design.
Note: To create a subdesign as a standalone design, make the subdesign as the
top-level design.
How do I control reference designators in subdesigns?
Packager-XL assigns reference designators to components in a subdesign bad on information contained in the P H Y S_D E S_P R E F I X directive and the S U B D E S I G N_S U F F I X property. The default reference designator assigned to subdesign instances has the following syntax:
<P H Y S_D E S_P R E F I X><R E F D E S_I N C R E M E N T><S D_S U F F I X_S E P A R A T O R><S U B D E S I G N_S U F F I X> where, the value of the P H Y S_D E S_P R E F I X property is obtained from the schematic, ptf files, the c h i p s.p r t file, or the project file. The value of R E F D E S_I N C R E M E N T is automatically assigned by Packager-XL. The default value of the S D_S U F F I X_S E P A R A T O R property is an underscore (_). The default value of the S U B D E S I G N_S U F F I X property is 1 and for each subquent component, the value increments by 1. To change this value, assign a new property to a subdesign instance by using the Text Attributes dialog box in Design Entry HDL. This makes the packaging assignments predictable as you can trace parts on the board to a specific subdesign instance.
The following table explains each individual ction of the reference designator and
how you can control it.
Section File where
the value is
stored Who
controls
the
assignment
定语从句语法>托收承付How can you change the value
P H Y S_D E S_P R E F I X schematic,
file c h i p s.p r t
file, p t f files,
or the project
file.Default is U.
You can
change it.
树仁大学Note: The
order of
缓解英语precedence
is
schematic,
ptf file,
c h i p s.p r t
file, and the
project file.
Enter a new value in the
Default Ref Des Pattern
postalcode
field in the Packager Setup
- Layout tab.
Attach the P H Y S_D E S_P R E F I X
property to a component.
Note: If there are multiple
instances of a component and
each instance is assigned a
P H Y S_D E S_P R E F I X property, then
Packager-XL will u only one
value. It will flag an error stating
that multiple P H Y S_D E S_P R E F I X
properties are found on the
schematic for the same physical
part and it will exit with error
status 1.四六级口语成绩查询
Change the value in the
a c care
c h i p s.p r t or ptf file for a
part.
R E F D E S_I N C R E M E N T Automatically
assigned by
Packager-XL
and is stored
in the
pxl.state file.Packager-
XL controls
新和中学
this value.
You cannot change this value.
ohmyladygagaS D_S U F F I X_S E P A R A T O R Project file Default is
an
underscore
(_).
You can
在线日语学校
change it.
Enter a new value in the
Subdesign Suffix Separator
field in the Packager Setup
- Subdesign tab.
Note: The above option is available in PSD 14.2 only.
Set the
S D _S U F F I X _S E P A R A T O R
directive using the following syntax:
S D _S U F F I X _S E P A R A T O R
character_name
where,
character_name reprents the new suffix for renaming reference designators.
S U B D E S I G N _S U F F I X Automatically assigned by Packager-XL and is stored in the pxl.state file.
Default is 1.You can change it.
Attach the S U B D E S I G N _S U F F I X
property to a component in Design Entry HDL.Using the SUBDESIGN_SUFFIX property
To assign a suffix of 5 to an instance of the b a s e _l e v e l subdesign, add the following property to the schematic block:
S U B D E S I G N _S U F F I X 5
This appends a suffix of _5 to all reference designators in that schematic block. For example, you may have the following values of reference designators in the subdesign:
U 1_5, U 2_5, a n d U 3_5
In the above values, the characters reprent the following:
Character
Reprents U
P H Y S _D E S _P R E F I X _S D _S U F F I X _S E P A R A T O R
5 (after the underscore)
S
U B D E S I G N _S U F F I X S U B D E S I G N _S U F F I X values must be unique across all subdesign
instances in the design, that is, you cannot have
S U B D E S I G N _S U F F I X = 1 on more than one subdesign instance
even when the subdesigns themlves are different
modules. This ensures that all reference designators are
unique.
If you add the same S U B D E S I G N_S U F F I X value on more than one instance, Packager-XL us the first S U B D E S I G N_S U F F I X property value it finds and creates a new value for the other instances while ignoring the value that you have assigned. Packager-XL also generates an error (269) stating that the S U B D E S I G N_S U F F I X value already exists, and therefore it ignores the S U B D E S I G N_S U F F I X value.
Note: If you do not u the S U B D E S I G N_S U F F I X property but u the F O R C E_S U B D E S I G N directive, the suffixes assigned by Packager-XL might get reassigned.
To prevent suffixes from being reassigned,
Specify the U S E_S U B D E S I G N directive when packaging new subdesign instances. Note: If you delete a subdesign instance, the suffix for the deleted instance is not reud.
In which situations should I u the GEN_SUBDESIGN,
FORCE_SUBDESIGN, and USE_SUBDESIGN directives?
The G E N_S U B D E S I G N is ud to create a subdesign, while the F O R C E_S U B D E S I G N and
U S E_S U B D E S I G N directives specify how to load the subdesign state file.
You u the G E N_S U B D E S I G N directive to specify the module (hierarchical block) for which you want to generate the subdesign state file. When this subdesign is ud in other designs, Packager-XL reads the subdesign state file to obtain information about the design.
Note: You can u the G E N_S U B D E S I G N directive only when the design name matches the root-level design. Packager-XL generates a subdesign state file only for the root-level design.
If you have generated a subdesign using the G E N_S U B D E S I G N directive and want to u it in the top-level design, you need to u either the F O R C E_S U B D E S I G N or
U S E_S U B D E S I G N directive. The primary difference between the two directives is in how often the data in the subdesign is read at the time of packaging the top-level design that contains the subdesign. If you u the F O R C E_S U B D E S I G N directive, Packager-XL reads the packaging information from the subdesign state file and applies it to every instance of the subdesign in the top-level (root) design. If you specify the
U S E_S U B D E S I G N directive, Packager-XL applies the packaging in the subdesign state file to only tho instances of the subdesign that have not been previously packaged in the top-level (root) design.
If you are generating the top-level design and including instances of the low-level design (which has its subdesign state file) in it for the first time, F O R C E_S U B D E S I G N and U S E_S U B D E S I G N behave similarly.
