专利名称：Zero idle time Z-state circuit for pha-sct
locked loops, delay-locked loops, and
天然染发万象城地址switching regulators
发明人：Sangbeom Parkcocksucker
申请号：US11009648
牛津词典年度词汇
申请日：20041209
公开号：US07132869B2
公开日：
20061107大学生英语作文网>波兰语
专利内容由知识产权出版社提供
专利附图：lucky意思
摘要：The four types of the zero idle time Z-state circuits are prented with an improvement in productivity, cost, chip area, power consumption, and design time. The
zero idle time Z-state circuits basically include a nsing gate, two stacked PMOS transistors, and a feedback line. The nsing gate ns a voltage at its input assuming no feedback is applied. Again, the corresponding output of two stacked PMOS transistors is assumed to be connected to the nsing input. Two stacked PMOS transistors generate a high impedance Z-state at its output according to the corresponding output of the nsing gate. Therefore, the feedback line keeps sampling the output and feeding back the output voltage to the nsing input. Conquently, the feedback configuration provides the initial output voltage, which is the midpoint voltage decided by the device aspect ratios of the nsing gate before normal operation starts in all three systems such as all kinds of pha-locked loops, delay-locked loops, and switching regulators. Thus, all the zero idle time Z-state circuits within all three systems make the initial condition clo to the expected condition in order to enable the systems to come into lock or regulation quickly. Thus, all the zero idle time Z-state circuits utilizing less than twelve transistors prented achieve a fast lock-in time, a solution for harmonic locking problem, a minimization of start-up time, a initial reduction in power and 雾霾天气注意事项
time, a significant reduction in design simulation time, an improvement in productivity, and a higher performance.
申请人：Sangbeom Park
地址：Tracy CA US
国籍：USillumina
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