A65-nm CMOS Temperature-Compensated Mobility-Bad Frequency Reference for Wireless
Sensor Networks
Fabio Sebastiano,Student Member,IEEE,Lucien J.Breems,Senior Member,IEEE,
KofiA.A.Makinwa,Fellow,IEEE,Salvatore Drago,Student Member,IEEE,Domine M.W.Leenaerts,Fellow,IEEE,
and Bram Nauta,Fellow,IEEE
Abstract—A temperature-compensated CMOS frequency refer-ence bad on the electron mobility in a MOS transistor is pre-nted.Over the temperature range from C to125C,the frequency spread of the complete reference is less than0.5% after a two-point trim and less than 2.7%after a one-point trim. The results make it suitable for u in Wireless Sensor Network nodes.Fabricated in a baline65-nm CMOS process,the150kHz frequency reference occupies0.2mm and draws42.6A from a 1.2-V supply at room temperature.
Index Terms—Charge carrier mobility,CMOS integrated circuits,crystal-less clock,frequency reference,low voltage, MOSFET,sigma-delta modulation,smart nsors,temperature compensation,tem
perature nsors,ultra-low power,wireless nsor networks.
I.I NTRODUCTION
W IRELESS Sensor Networks(WSN)are bad on small, cheap and energy efficient nodes.Since the largest frac-tion of the energy ud in each node is spent listening to the channel,synchronous networks are employed to shorten this wasted time[1].In that ca,the receiver predicts the timeslot that the transmitter will u and turns itlf off when no in-coming signal is expected.The duty-cycle of the receiver can be lower if the timeslot is predicted with a smaller ,if a more accurate time reference is available.Accuracies of a few ppm can be achieved by crystal-controlled oscillators(XCOs), but since such external components should be avoided to reduce the cost and size of the nodes,accuracy must be given up for the sake of integration.
The tradeoff between integration and time/frequency accu-racy is also prent in the RF front-end.While commercial com-munication systems require high frequency accuracy,radios for
Manuscript received November22,2010;revid January27,2011;accepted February24,2011.Date of publication May16,2011;date of current version June24,2011.This paper was approved by Guest Editor Angel Rodriguez-Vazquez.This work was supported by the European Commission in the Mari
e Curie project TRANDSSAT–2005-020461.
F.Sebastiano,L.J.Breems,S.Drago,and D.M.W.Leenaerts are with NXP Semiconductors,5656AE Eindhoven,The Netherlands(e-mail:fabio.).
K.A.A.Makinwa is with the Electronic Instrumentation Laboratory,Delft University of Technology,Delft,The Netherlands.
B.Nauta is with the IC Design Group,CTIT Rearch Institute,University of Twente,Enschede,The Netherlands.
Color versions of one or more of thefigures in this paper are available online at ieeexplore.ieee.
Digital Object Identifier10.1109/JSSC.2011.2143630WSN can be optimized to relax such specifications and so fre-quency accuracies in the order of only a few percent are needed [1]–[3].Thus,it is interesting to investigate the level of accu-racy that can be reached without external components,while also operating at the low voltage and power levels typical of WSN.Moreover,since CMOS RF circuits can be implemented with higher power efficiency in deep-submicron process[4],
it is appropriate to pay attention to the possibility of fully in-tegrating the entire node,including the frequency reference,in such process.
Recently,much work has been devoted to implementing fully integrated frequency references in standard microelectronic technologies.LC oscillators[5]can provide accuracy and pha noi performances comparable to XCOs;however,their power consumption can hardly be reduced below100W due to the limited quality factor of integrated inductors and the pos-sible need for high-speed frequency dividers.Fully integrated frequency references bad on ring oscillators[6]and silicon thermal diffusivity[7]are quite accurate,but dissipate veral milliwatts of power.RC oscillators can achieve inaccuracies less than1%while consuming less than200W[8],[9],but their accuracy relies on the availability of on-chip resistors with low or,at least,accurately defined temperature coefficients. As an alternative,the mobility of the charge carriers in a MOS transistor can be employed as a reference in a low-power fully integrated oscillator which does not require accurate components other than MOS transistors.It exhibits low process spread and,although its temperature dependence is large(ap-proximately proportional to,where is the absolute temperature),it is well defined for a given process and thus can be compensated for.The effect of process spread can then be removed by a one-point or two-point temperature calibration. In this paper,we explore the level of accuracy tha
t can be achieved by a fully integrated temperature-compensated oscillator that is referenced to the electron mobility[10].The mobility-bad oscillator prented in[11]and the temperature nsor prented in[12]have been integrated on the same die and combined to realize a novel temperature compensation scheme.Experimental validation of this approach will be provided,demonstrating that,after a two-point calibration,a frequency spread of less than0.5%can be achieved over the military temperature range.Section II describes the architec-ture of the overall frequency reference.The implementation of the main blocks composing the frequency reference(mo-
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bility-referenced oscillator,temperature nsor and temperature compensation)is described in detail in Section III.Experi-mental results are shown in Section IV and conclusions are given in Section V.
II.S YSTEM A RCHITECTURE
The core of the propod frequency reference is a current-controlled relaxation oscillator,in which the current is propor-tional to the electron mobility.Conquently,as explained in details in Section III-A,its output frequency has the same tem-perature dependency as the electron mobility and so tempera-ture compensation is needed.This can be implemented either in analog or in digital way.An
analog compensation can be real-ized by adjusting one of the many analog control variables pos-sible in the oscillator.For example,the control current of the oscillator can be implemented as the sum of the mobility-de-pendent current and a current with a complementary temper-ature dependency.This would be fairly easy if a physical ef-fect with such a complementary temperature dependance would exist.However,it does not and the generation of a suitable cur-rent would increa circuit complexity and be subject to errors which would lower the accuracy of the frequency reference. Digital temperature compensation schemes do not suffer from the problems.It can be easily implemented by dividing or multiplying the oscillator frequency by a temperature-de-pendent factor.Operations in the time domain(frequency multiplication and division)are well suited to deep-submicron implementation,since the inherent speed of the process can be exploited to achieve accurate performances by reducing the delays in any time operation.Moreover,as will be explained in the following,a large part of the compensation can be implemented by re-using circuit blocks already prent in the system.This minimizes circuit overhead and,conquently, power consumption.
Fig.1shows the propod compensation schemes.In Fig.1(a),the output frequency of the mobility-bad oscillator is ud as the reference of an integer-pha-locked loop(PLL),compod of a pha detector(PD),a loopfilter, a voltage-controlled oscillator(VCO)and an divider.Via a pre-determined co
mpensation curve,the digital output of a tem-perature nsor(TS)is mapped to the divider factor,in such a way that the output frequency remains constant over temperature.In Fig.1(b),is obtained by direct division of by a temperature-dependent.As already mentioned in the introduction,a WSN node needs both a low-frequency reference for time synchronization of the network protocol and a high-frequency reference for RF communication.Thus,most of the blocks for temperature compensation in Fig.,the PLL to generate and the divider to generate,are al-ready prent in the WSN node.If both systems of Fig.1would be integrated in the WSN node,only the nonlinear mapping function should be added to obtain both the high-frequency and low-frequency temperature-independent references.
In order to simplify hardware implementation,it would be convenient for both and to be integers.To make
the Fig.1.Architectures for the frequency reference with temperature compensa-tion implemented by means of(a)frequency multiplication and(b)frequency division.
effect of temperature compensation negligible in the total accu-racy,the quantization error due to the temperature compensa-tion should be low enough,which can be expresd,for
and integers,as
(1)
(2) where is the minimum factor needed to achieve the re-quired resolution,is the aimed accuracy for the whole ref-erence and a factor10has been assumed between the refer-ence accuracy and the quantization error of the compensation scheme,to make the latter negligible.Considering that
syllableand with,the fol-lowing inequality must be satisfied
(3) It has been proven that WSNs can tolerate,while adopting an RF frequency of the order of1GHz and using time spans between10ms and100ms for the network synchroniza-tion[1],[2].It follows from(3)that the oscillator frequency must be in the range between1MHz and10kHz,while keeping at least10bits of resolution for the divider ratios.A value of kHz is then ud in this work.Since the accur
acy of the propod mobility-bad reference can be demonstrated by any of the two systems of Fig.1,only the system in Fig.1(b) has been implemented and it is discusd in the following.
Fig.2.(a)Mobility-referenced oscillator and(b)its waveforms,from[11].
III.C IRCUIT I MPLEMENTATION
A.Mobility-Bad Oscillator
A simplified schematic of the mobility-bad frequency refer-ence is shown in Fig.2(a).As shown in[11]and with reference to Fig.2,the oscillation frequency is
(4) where is the electron mobility,is the oxide capacitance per unit area,and are the width and length of and
.If,and are reference volt-ages(or if at least they are proportional),then has the same temperature dependence as.The typical measured output frequency of the mobility-bad oscillator is shown in Fig.3. The plot,obtained by measurement of the test chip described in Section IV,is shown here to illustrate the temperature depen-dence of,which,in turn,is needed in the next ction to derive the requirements for the TS.
mikro
好听的抒情英文歌曲B.Temperature Sensor
1)Requirements:Besides the need for a low-power low-voltage circuit implementation,the main specifications of the TS are accuracy and conversion rate.With regards to accuracy, if the reading of the TS has an error,the error in the com-pensated frequency is given,for an ideal temperature com-pensation,by
(5) Using the data from Fig.3,the error in the compensated fre-quency for different values of is shown in Fig.4.As for
the Fig.3.Uncompensated oscillator output frequency(
).
Fig.4.Accuracy of the output frequency after compensation using a tempera-ture nsor with an accuracy.
quantization error introduced by the compensation scheme,the error is kept to about0.1%,which corresponds to C. The conversion rate must be adequate to the temperature variations expected in the particular application.A slow nsor might not be able to accurately track such variations and would thus introduce extra readout errors.Temperature variations can be caud either by lf-heating of the die or by environmental variations.Thefirst can be neglected for a WSN node,since lf-heating is limited to few hundredths of a degree Celsius for power dissipations of a few100W,considering a thermal resistance between die and ambient in the order1of100C. The latter is limited to a variation of a few degrees in a time span ranging from conds to minutes for typical WSN applica-tions,such as environmental monitoring.Moreover,the thermal mass of the silicon die itlf()combined with the thermal resistance of the package()filters the high-frequency components of environmental variations down to few hertz.2
1A package thermal resistance in the order of100C is typical for the most common IC packages
mapguide
2For a typical silicon die of1mm area, C.Consid-ering a simple lumped-element thermal model,this together with
C results in a3-Hz cut-off frequency.
enjoyonelfFig.5.Simplified schematic of the bandgap temperature nsor(from[12]).
2)Propod Temperature Sensor:Several nsing princi-ples have been propod for deep-submicron CMOS temper-ature nsors[14]–[17].However,only bandgap temperature nsors achieve an accuracy below1C without the need for an expensive multi-point temperature calibration and with a power consumption below100W[18].Conquently,a bandgap TS has been ud in this work.
The propod bandgap bad TS is shown in Fig.5[12]. When are both high,the vertical NPN are biad by the PMOS current sources array at a1:4collector current ratio to produce a proportional-to-absolute-temperature(PTAT) difference between their ba emitter voltages. When()is high and()is low,()is biad by afixed current and the ba-emitter junction of()is shorted to produce().The feed-back loops comprising the amplifiers and the common-source buffers compensate the ba current of,so that neither nor depends on the bipolar current gain.Moreover, the two loops decrea the impedance at the collectors of, byfixing the collector voltages equal to the reference voltage .To prevent the capacitive load of the analogue-to-dig-ital converter from making the loops unstable,diode-connected are added to lower the impedance at the ba of.
barrel
Afirst-order analog-to-digital converter is ud to pro-duce an output bitstream who average reprents the TS output.The bitstream average is extracted by a cascaded decimationfilter.The switched-capacitor integrator in the integrates when and when.Since the negative feedback forces the average integrated voltage to be zero,the bitstream average is
(6) Although is a nonlinear function of temperature,the biasing of the NPNs has been chon[12]such that a function that is PTAT can be obtained by applying the transformation
(7)C.Temperature Compensation
To investigate the level of accuracy reachable by the mo-bility-bad frequency reference,two distinct and independent temperature compensation schemes have been implemented,re-quiring either a single-point trim or a two-point trim.While the cost of a single-point trim is relatively low,the cost of a two-point trim can make the whole reference even more expen-sive than XCOs.However,its reduced size,thanks to the full in-tegration,makes it the preferred choice in veral applications. For both schemes,the resolution of the divider ratio has been kept to13bits.As discusd in Section II,even a resolu-tion of approximately10bits is high enough when aiming for accuracy in the order of1%.However,a higher resolution is preferred to show that accuracy lower than1%can be reached o
ver a temperature range narrower than the industrial range. For a single-point trim,the oscillation frequency of each sample at the trim temperature is measured.A venth-order polynomial,who coefficients arefixed for all the samples,is then obtained via a batch calibration.The divider factor is computed as
(8) where ms is the nominal frequency of ,the desired output frequency.tf是什么意思
For a two-point trim,the following procedure is adopted.The oscillator frequency and the on-chip TS decimated output are measured at two different temperatures,and. This data is ud to interpolate the frequency using the inter-polant
(9) where is computed from the TS output using(7)and and are the trim parameters for each sample.A fourth-order polynomial is obtained from batch calibration so that the divider factor computed for each sample is
(10)
Fig.6.Die micrograph of the test
chip.
Fig.7.System block diagram of the mobility-bad frequency reference showing the partition in the implementation between on-chip circuitry and FPGA.
The polynomial 3is required to compensate for the fact that the power-law interpolant in (9)only approximately de-scribes the temperature dependence of the electron mobility,es-pecially over a wide temperature range.
In terms of complexity,the trimming procedure requires only the measurement of at one temperature for the single-point trim,and the measurement of ,and at such temperatures for the two-point trim.The trim parameter and can be computed by fitting an exponential function through the points and .Finally,note that the computation of requires only basic mathematical ,computation of polynomial,mul-tiplication and rai to the power,which are well-suited for im-plementation in a deep-submicron CMOS process.
IV .E XPERIMENTAL R ESULTS
The frequency reference was fabricated in a standard 65-nm CMOS process (Fig.6).The circuit occupies 0.2mm (0.1mm for the oscillator and 0.1mm for the TS)and us only 2.5-V I/O thick oxide MOS devices.For flexibility,some control logic,the TS’s sinc decimation filter (employing 6000bitstream sam-ples to produce one temperature reading)and the reference volt-ages (,,)were implemented off-chip.The reference draws 42.6A (34.3A for the oscillator and 8.3A for the TS)from a
1.2-V supply at room temperature.The supply nsi-tivity is 1.2%/V.In order to flexibly test different compensation schemes,the temperature compensation scheme has been im-plemented in an off-chip FPGA,as shown in Fig.7.However,if
3Note
that the order of the polynomials and is the minimum
required for the error due to the nonlinearity of to be negligible compared to the spread among the samples.
the temperature compensation had been implemented on-chip,its consumption would have been negligible.From simulations,the power consumption of a 13-bit frequency divider imple-mented in 65-nm CMOS is below 0.3W at room temperature for an input frequency of 150kHz and a 1.2-V supply.The non-linear-mapping block consumption would also be low consid-ering that the value of must be updated only at the rate of the TS,which is in the order 4of 1Hz.
Measurements on 12samples from one batch were performed over the temperature range from 70C to 125C using a temperature-controlled oven.For tho measurements,the ref-erence voltages were t to V,V,and
V and the supply of the comparator of Fig.2(a)has
been raid to 1.5V.This ensures that MOS capacitor and
are biad in deep inversion to prevent the spread of their threshold voltage from affecting the spread of the reference,and thus masking the inherent accuracy of the mobility-bad ref-erence.The temperature of the samples was measured using a Pt100platinum thermometer and compared to the temperature reading of the on-chip TS.The TS shows a spread on of 0.5C ()over the range from 70C to 125C.
Fig.8shows the uncompensated output frequency of the oscillator.At room temperature,its maximum deviation from the average is 6%.The temperature compensation has then been implemented off-line in Matlab.First,the samples were trimmed at 22C and compensated with an external Pt100and an ideal temperature compensation curve.In tho conditions,the maximum error is 2.6%over the military range from 55C to 125C.Then,the compensation polynomial
(e Section III-C)was extracted from batch calibration of the 12devices.After a single-point trim at 22C,the error when compensating with the on-chip TS is less than 2.7%(Fig.9).Finally,a two-point trim at 27C and 105C was employed and the error improved to 0.5%using another compensating pol
ynomial (e Section III-C)extracted from a batch calibration of the 12devices (Fig.10).The temperature of the two trimming points has been chon to optimize the accuracy of the frequency ref-erence over the temperature range of interest.For the adopted compensation schemes,the resolution of the integer divider factor in Fig.1has been limited to 13bits.
In order to study the dynamic performance of the temperature compensation,one of the samples already tested in the tempera-ture-controlled oven has been tested under the effect of fast tem-perature variations.Fig.11shows the static frequency error of the tested sample over the temperature ,the frequency error under static temperature conditions.Note that the lected sample is among tho with lowest static error,so that the error due to the dynamic behavior can be more easily obrved.In this ca,real-time temperature compensation has been performed on the FPGA,while the sample (packaged in a ceramic DIP28package)was heated by a flux of hot air.For tho measure-ments,the reference voltages were t to V,
V and V,kHz and all supplies were t to 1.2V.The TS was sampled at 3Sa/s.The
4The
update rate of depends on the temperature variations rate in the
chon application.
Fig.8.Uncompensated oscillator output frequency (
).
Fig.9.Frequency error of the reference after single-point
trim.
pana
Fig.10.Frequency error of the reference after two-point trim.
modulator in the TS is operated as an incremental converter:it is
first ret and a temperature reading is produced after .In the next period ,such temperature reading is pro-duced to compute and compensate .The output fre-quency is then affected by errors due to the delay of
in the temperature compensation.Fig.12shows the measured time-domain waveforms acquired by the FPGA,including the temperature reading
of the on-chip TS,the period of and
Fig.11.Frequency error of the sample ud for time-domain measurements (after a single-point trim at room temperature).
the divider ratio .When hot air is applied,the on-chip tem-perature ris from room temperature to approximately 100C with an exponential respon with time constant s.Due to the fast temperature variation,a step is obrved in the oscil-lation period due to the temperature compensation delay.The amplitude of the step can be computed by considering the tem-perature reading error due to the dela
y and by applying (5).The amplitude of the step is given by
(11)
where is the oscillation period of the output signal (
)in the steady state,is the equivalent temperature error due to the compensation delay and 75C is the step in the die temperature.has been calculated by considering an expo-nential ttling of the temperature with time constant .Using the data from (5)and the data from Fig.4,0.3ms,which is in good agreement with the value measured in Fig.12.When the flow of hot air stops,the temperature drop exponen-tially to the room temperature.5Even if a negative step in the os-cillation period is expected at the ont of the cooling,it is not visible in the measurements.This is becau the cooling tran-sient is slow enough to make the dynamic error much smaller than the static error reported in Fig.11.The oscillation period is also affected by random noi with standard deviation of 0.1%,in agreement with the long-term jitter measurements shown pre-viously in [11].This proves that also under excitation with large and fast temperature variations,the frequency reference error is kept in the order of 1%.
The frequency reference’s performance is summarized in Table I and compared to other low-power f
ully integrated CMOS frequency references.The silicon area and the power consumption of the propod frequency reference are compa-rable to the other designs in Table I,even if a fair comparison isforced
5The
time constant of the exponential ttling is in this ca s due
adjto the lack of induced air flow on the sample and the conquent increa in
thermal resistance
.
