STM32F103VET6——ADC库函数结构体STM32F103VET6——ADC库函数结构体
参考 《STM32F10x-英⽂参考⼿册》
《零死⾓玩转STM32—F103指南者》
秉⽕视频教程
F103库函数
结构体
typedef struct
{
uint32_t ADC_Mode;/*!< Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode;/*!< Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be t to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode;/*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be t to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv;/*!< Defines the external trigger ud to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign;/*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel;/*!< Specifies the number of ADC channels that will be converted
using the quencer for regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
外国电影推荐ADC_mode
#define ADC_Mode_Independent((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult((uint32_t)0x00050000)
#define ADC_Mode_RegSimult((uint32_t)0x00060000)
#define ADC_Mode_FastInterl((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig((uint32_t)0x00090000)
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
ADC_ExternalTrigConv
//ADC_external_trigger_sources_for_regular_channels_conversion
#define ADC_ExternalTrigConv_T1_CC1((uint32_t)0x00000000)/*!< For ADC1 and ADC2 */
课程思维导图
#define ADC_ExternalTrigConv_T1_CC2((uint32_t)0x00020000)/*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T2_CC2((uint32_t)0x00060000)/*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T3_TRGO((uint32_t)0x00080000)/*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T4_CC4((uint32_t)0x000A0000)/*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO((uint32_t)0x000C0000)/*!< For ADC1 and ADC2 */
#define ADC_ExternalTrigConv_T1_CC3((uint32_t)0x00040000)/*!< For ADC1, ADC2 and ADC3 */ #define ADC_ExternalTrigConv_None((uint32_t)0x000E0000)/*!< For ADC1, ADC2 and ADC3 */
#define ADC_ExternalTrigConv_T3_CC1((uint32_t)0x00000000)/*!< For ADC3 only */
#define ADC_ExternalTrigConv_T2_CC3((uint32_t)0x00020000)/*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_CC1((uint32_t)0x00060000)/*!< For ADC3 only */
#define ADC_ExternalTrigConv_T8_TRGO((uint32_t)0x00080000)/*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC1((uint32_t)0x000A0000)/*!< For ADC3 only */
#define ADC_ExternalTrigConv_T5_CC3((uint32_t)0x000C0000)/*!< For ADC3 only */
Figure 2-9
ADC_data_align
#define ADC_DataAlign_Right((uint32_t)0x00000000)
#define ADC_DataAlign_Left((uint32_t)0x00000800)
常⽤库函数
* @brief Initializes the ADCx peripheral according to the specified parameters
* in the ADC_InitStruct.
* @param ADCx: where x can be 1, 2 or 3 to lect the ADC peripheral.
* @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
* the configuration information for the specified ADC peripheral.
* @retval None
*/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
{
uint32_t tmpreg1 =0;
uint8_t tmpreg2 =0;
格式
/* Check the parameters */
asrt_param(IS_ADC_ALL_PERIPH(ADCx));
asrt_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
asrt_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
asrt_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
asrt_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
asrt_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
asrt_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
/*---------------------------- ADCx CR1 Configuration -----------------*/
英语字母书写/* Get the ADCx CR1 value */
tmpreg1 = ADCx->CR1;
/* Clear DUALMOD and SCAN bits */
tmpreg1 &= CR1_CLEAR_Mask;
/* Configure ADCx: Dual mode and scan conversion mode */
/* Set DUALMOD bits according to ADC_Mode value */
/* Set SCAN bit according to ADC_ScanConvMode value */
tmpreg1 |=(uint32_t)(ADC_InitStruct->ADC_Mode |((uint32_t)ADC_InitStruct->ADC_ScanConvMode <<8)); /* Write to ADCx CR1 */
ADCx->CR1= tmpreg1;
/*---------------------------- ADCx CR2 Configuration -----------------*/
/* Get the ADCx CR2 value */
tmpreg1 = ADCx->CR2;
/* Clear CONT, ALIGN and EXTSEL bits */
tmpreg1 &= CR2_CLEAR_Mask;
/* Configure ADCx: external trigger event and continuous conversion mode */
/* Set ALIGN bit according to ADC_DataAlign value */
/* Set EXTSEL bits according to ADC_ExternalTrigConv value */
/* Set CONT bit according to ADC_ContinuousConvMode value */
tmpreg1 |=(uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode <<1));
/* Write to ADCx CR2 */
ADCx->CR2= tmpreg1;
/*---------------------------- ADCx SQR1 Configuration -----------------*/
/* Get the ADCx SQR1 value */
tmpreg1 = ADCx->SQR1;
/* Clear L bits */
tmpreg1 &= SQR1_CLEAR_Mask;
/* Configure ADCx: regular channel quence length */
/* Set L bits according to ADC_NbrOfChannel value */
tmpreg2 |=(uint8_t)(ADC_InitStruct->ADC_NbrOfChannel -(uint8_t)1);
tmpreg1 |=(uint32_t)tmpreg2 <<20;
/* Write to ADCx SQR1 */
ADCx->SQR1= tmpreg1;
}udto的用法
* @brief Configures the ADC clock (ADCCLK).
* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
* the APB2 clock (PCLK2).
* This parameter can be one of the following values:
* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
* @retval None
*/
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
{
uint32_t tmpreg =0;
/* Check the parameters */
asrt_param(IS_RCC_ADCCLK(RCC_PCLK2));
tmpreg =RCC->CFGR;
/* Clear ADCPRE[1:0] bits */
tmpreg &= CFGR_ADCPRE_Ret_Mask;
/
* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
tmpreg |=RCC_PCLK2;
/* Store the new value */
RCC->CFGR= tmpreg;
}
/**
* @brief Configures for the lected ADC regular channel its corresponding
* rank in the quencer and its sample time.
* @param ADCx: where x can be 1, 2 or 3 to lect the ADC peripheral.
* @param ADC_Channel: the ADC channel to configure.
* This parameter can be one of the following values:
* @arg ADC_Channel_0: ADC Channel0 lected
* @arg ADC_Channel_1: ADC Channel1 lected
* @arg ADC_Channel_2: ADC Channel2 lected
* @arg ADC_Channel_3: ADC Channel3 lected
* @arg ADC_Channel_4: ADC Channel4 lected
* @arg ADC_Channel_5: ADC Channel5 lected
* @arg ADC_Channel_6: ADC Channel6 lected
* @arg ADC_Channel_7: ADC Channel7 lected
* @arg ADC_Channel_8: ADC Channel8 lected
* @arg ADC_Channel_9: ADC Channel9 lected
* @arg ADC_Channel_10: ADC Channel10 lected
* @arg ADC_Channel_11: ADC Channel11 lected
* @arg ADC_Channel_12: ADC Channel12 lected
* @arg ADC_Channel_13: ADC Channel13 lected
* @arg ADC_Channel_14: ADC Channel14 lected
* @arg ADC_Channel_15: ADC Channel15 lected
* @arg ADC_Channel_16: ADC Channel16 lected
* @arg ADC_Channel_17: ADC Channel17 lected
* @param Rank: The rank in the regular group quencer. This parameter must be between 1 to 16.
* @param ADC_SampleTime: The sample time value to be t for the lected channel.
* This parameter can be one of the following values:
* @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
* @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
* @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
* @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
* @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
* @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
* @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
* @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
效劳* @retval None
*/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) {
uint32_t tmpreg1 =0, tmpreg2 =0;
/* Check the parameters */
asrt_param(IS_ADC_ALL_PERIPH(ADCx));
asrt_param(IS_ADC_CHANNEL(ADC_Channel));
asrt_param(IS_ADC_REGULAR_RANK(Rank));
asrt_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
/* if ADC_Channel_10 ... ADC_Channel_17 is lected */
if(ADC_Channel > ADC_Channel_9)
{
/* Get the old register value */
tmpreg1 = ADCx->SMPR1;
/* Calculate the mask to clear */
tmpreg2 = SMPR1_SMP_Set <<(3*(ADC_Channel -10));
/* Clear the old channel sample time */
tmpreg1 &=~tmpreg2;
/* Calculate the mask to t */
tmpreg2 =(uint32_t)ADC_SampleTime <<(3*(ADC_Channel -10)); /* Set the new channel sample time */
tmpreg1 |= tmpreg2;
/* Store the new register value */
ADCx->SMPR1= tmpreg1;
}
el/* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Get the old register value */
tmpreg1 = ADCx->SMPR2;
雅安地震感人图片/* Calculate the mask to clear */
tmpreg2 = SMPR2_SMP_Set <<(3* ADC_Channel);
/* Clear the old channel sample time */
tmpreg1 &=~tmpreg2;
/* Calculate the mask to t */
tmpreg2 =(uint32_t)ADC_SampleTime <<(3* ADC_Channel);
/* Set the new channel sample time */
tmpreg1 |= tmpreg2;
ticketing/* Store the new register value */
ADCx->SMPR2= tmpreg1;gre班课
}
/* For Rank 1 to 6 */
if(Rank <7)
{
/* Get the old register value */
tmpreg1 = ADCx->SQR3;
/* Calculate the mask to clear */
tmpreg2 = SQR3_SQ_Set <<(5*(Rank -1));
/* Clear the old SQx bits for the lected rank */
tmpreg1 &=~tmpreg2;
/
* Calculate the mask to t */
tmpreg2 =(uint32_t)ADC_Channel <<(5*(Rank -1));
/* Set the SQx bits for the lected rank */
tmpreg1 |= tmpreg2;
/* Store the new register value */
rbdADCx->SQR3= tmpreg1;
}
/* For Rank 7 to 12 */
el if(Rank <13)
{
/* Get the old register value */
tmpreg1 = ADCx->SQR2;
/* Calculate the mask to clear */
tmpreg2 = SQR2_SQ_Set <<(5*(Rank -7));
/* Clear the old SQx bits for the lected rank */
tmpreg1 &=~tmpreg2;
/* Calculate the mask to t */
tmpreg2 =(uint32_t)ADC_Channel <<(5*(Rank -7));
/* Set the SQx bits for the lected rank */
tmpreg1 |= tmpreg2;
/* Store the new register value */
ADCx->SQR2= tmpreg1;
}
/* For Rank 13 to 16 */
el
{
/* Get the old register value */
tmpreg1 = ADCx->SQR1;
