gaddafi
Catapult C Synthesis Whitepaper Advanced Clock Gating Techniques in Catapult C Synthesis
Last Modified: June 24, 2009
Today, power consumption has become a quality metric of SoC designs as important as area and performance. Electronic System Level (ESL) design methodologies enable power consumption optimization opportunities unreachable for traditional RTL design methods. The Catapult C Synthesis tool, in addition to its power-aware architecture exploration capabilities, employs veral power optimization methods to deliver designs with minimum power dissipation.This whitepaper discuss one of the most important power optimization techniques ud in Catapult C Synthesis – advanced clock gating optimization and analysis.
雅思成绩查询官网
<
Copyright © 2009 Mentor Graphics Corporation. All rights rerved.
This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this
Introduction
Clock gating is the most important and widely
ud technique of reducing power consumption of digital designs. This technique ensures that clock edges are applied to a register only in clock cycles in which the register actually needs updating, thus allowing substantial savings in dynamic power consumption. In addition, clock gating typically leads to overall design area
reduction, which decreas design’s leakage (or static) power.
Copyright © 2009 Mentor Graphics Corporation. Mentor products and process are registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners. Corporate Headquarters Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777 Phone: 503-685-7000 Silicon Valley Mentor Graphics Corporation
1001 Ridder Park Drive
San Jo, California 95131 USA Phone: 408-436-1500 Europe
Mentor Graphics Deutschland GmbH Arnulfstras 201 80634 Munich Germany
Pacific Rim
Mentor Graphics Taiwan Room 1001, 10F,
International Trade Building
No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Japan
Mentor Graphics Japan Co., Ltd. Gotenyama Garden
7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 -0001 Japan
As a rule, gated clock inrtion is performed automatically by RTL synthesis tools such as PowerCompiler or RTL Compiler. In order to enable the tools to successfully find registers, to which clock gating can be applied, RTL
designers u an “explicit enable signal” coding style in their VHDL or Verilog source code. This coding style is illustrated in Figure 1.
This coding style does not explicitly force an RTL synthesis tool to u clock gating techniques for the node q , but rather allows the tool to choo between two possible implementation options, which are shown in Figure 2 – recirculating register with a feedback multiplexer or ICGC (Integrated Clock Gating Cell).
Deciding which particular implementation will best suit a particular register of a design depends upon many factors. From the standpoint of minimizing area, ICGC implementation typically delivers better results, especially for multi-bit registers. Choosing one particular implementation bad on a power consumption point of view is a more
北京托福考试取消Verilog
always@(podge clk) begin
if (rst == 1’b1) q <= 1’b0;
el if (en == 1’b1) q <= d; end
VHDL
wait until clk’event and clk=1; if (rst = ‘1’) then q <= ‘0’;
采用英语
el if (en = ‘1’) q <= d; end if;
Figure 1 Explicit Enable Signal for Clock Gating Inrtion
difficult task, which requires vector-bad power analysis to be performed for each and every register in the design. This is the reason why registers that have an explicit enable signal are often called “clock gating candidates ”. This name simply reflects the fact that it is impossible to decide in advance of RTL synthesis and power analysis whether clock gating should be ud for a particular register or not.
Clock Gating in Catapult C
fobshanghai
Synthesis
Copyright © 2009 Mentor Graphics Corporation. Mentor products and process are registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners. Corporate Headquarters Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777 Phone: 503-685-7000 Silicon Valley Mentor Graphics Corporation
1001 Ridder Park Drive
San Jo, California 95131 USA Phone: 408-436-1500 Europe
Mentor Graphics Deutschland GmbH Arnulfstras 201 80634 Munich Germany
Pacific Rim
Mentor Graphics Taiwan Room 1001, 10F,
International Trade Building
No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Japan
Mentor Graphics Japan Co., Ltd. Gotenyama Garden关于朋友的英语谚语
7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 -0001 Japan
Catapult C Synthesis is a high-level synthesis tool that reads ANSI C++ and produces VHDL or
Verilog RTL designs which are tuned (scheduled) for the specific RTL synthesis tool and technology library in u. Therefore, following the best design practices ud by RTL designers today, Catapult neither directly instantiates integrated clock gating cells nor decides whether a clock gating cell
should be ud in each particular ca. Instead, Catapult C Synthesis employs a more flexible approach to clock gating – it produces as many registers with explicit enable signals as possible, leaving power analysis and RTL synthesis tools to decide whether the ICGC implementation is required or not. In other words, registers
generated by Catapult with an explicit enable are simply clock gating candidates.
In order to produce the maximum possible number of clock gating candidates, Catapult
performs special clock gating optimization , which examines every register in the design and extracts feedback datapaths out of the logic cones to generate logic conditions that may be ud as explicit enable signals with maximum possible efficiency.
Typical Area and Power Savings
The result of this optimization is a “clock gating friendly” RTL netlist that produces the best
achievable clock gating quality regardless of the RTL synthesis tool in u or number of levels in clock gating scheme to infer in the gate-level netlist. Plea note that power savings due to clock gating are design and test vector dependent. As a rule, designs with full
handshaking at all I/Os are more likely to benefit from Catapult clock gating optimization.
The quality of results produced by the Catapult clock gating optimization are much better than tho potentially reachable if extraction of explicit enable signals is done by an RTL synthesis tool alone, simply becau Catapult, being a high-level synthesis tool, us its “knowledge” of the design’s quential properties to perform this optimization. This “knowledge” is usually unavailable to RTL synthesis tools or can be easily misd by designers hand-coding their RTL.
Although area and power consumption improvements due to Catapult clock gating optimization may significantly vary from ca to ca, on average, it leads to 10-15% reduction in design area and to 20-40% savings in dynamic power consumption. The latter number in some cas can reach 90% or more.
the story
Below is a table showing improvements in area and power for a test suite, which includes typical designs for wireless networking and video
processing applications. The results have been produced with a 65 nm standard cell library. The area and power consumption numbers were reported for gate-level netlists by RTL Compiler after synthesis. The comparison was performed by turning on and off the Catapult clock gating optimization control while all other high-level and RTL synthesis constraints remained the same in both cas.
Test Ca
RTL Compiler
Area
RTL Compiler
Power
当你离开时OFDM Interleaver -10.9% -83.2% OFDM De-Interleaver
-12.8% -80.9% OFDM Reed-Solomon Encoder -5.5% -79.6% OFDM Reed-Solomon Decoder -15.2%
-76.2% OFDM Viterbi Decoder -13.0% -96.4% H.264 De-blocking Filter -5.8% -69.5% H.264 Inter-Chroma Predictor
-9.4%
-93.2%
Copyright © 2009 Mentor Graphics Corporation. Mentor products and process are registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners. Corporate Headquarters Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777 Phone: 503-685-7000 Silicon Valley Mentor Graphics Corporation
1001 Ridder Park Drive
San Jo, California 95131 USA Phone: 408-436-1500 Europe
Mentor Graphics Deutschland GmbH Arnulfstras 201 80634 Munich Germany
统考英语bPacific Rim
Mentor Graphics Taiwan Room 1001, 10F,
International Trade Building
No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Japan
Mentor Graphics Japan Co., Ltd. Gotenyama Garden
attention是什么意思
7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 -0001 Japan
