专利名称：ELAPSED TIME COUNTER
发明人：SATOU FUMITAKA,MURAYAMA MASAKI 申请号：JP12074978
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申请日：19780930
sweet dream公开号：JPS5547478A
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圣诞祝福 英文
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摘要：PURPOSE:To eliminate timer enable flip-flop in an elapd time counter provided in a computer or the like by detecting that the content of a timer register becomes negative to thereby automatically stop the counting operation. CONSTITUTION:A timer register 11 t in advance with positive value subtracts the output of a circuit 14 for detecting that the content of the timer register is negative maximum value by the output form an oscillator 13 to detect that the content becomes zero by a detector 15 so as to produce a timer interrupt request signal 16. The timer register continues subtraction while the signal 16 is queued, and when the difference becomes negative maximum value, the output of the circuit 14 becomes zero to thereby clo an AND gate 12. When positive value is t in the register 11, the elapd time counter again starts operation.
dropby申请人：TOKYO SHIBAURA ELECTRIC CO
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