同步复位和异步复位的优缺点
西安学大教育>行李房Advantages of synchronous rets优点的英文
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1. Synchronous ret logic will synthesize to smaller flip-flops, paticularly if the ret if gated with the logic generating the d-input.
北大青鸟it培训2. Synchronous rets generally insure that the circuit is 100% synchronous.
3. In some designs, the ret must be generated by a t of internal conditions. A synchronous ret is recommended for the types of designs becau it will filter the logic equation glitches between clocks.
Disadvantages of synchronous rets
1. Not all ASIC libraries have flip-flops with built-in synchronous rets. However since synchronous ret is just another data input, you don't really neea a special flop. The ret logic can easily be synthesized outside the flop itlf.
gril2. Synchronous rets may need a pul stretcher to guarantee a ret pul width wide enough to ensure ret is prent during an active edge of the clock.
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3. By its very nature, a synchronous ret will require a clock in order to ret the circuit. This may not be a disadvantage to some design styles but to others, it may be an annoyance.
Advantages of asynchronous rets
1. The beggest advantage to using asynchronous rets is that, as long as the vendor library has asynchronously ret-able flip-flops, the data path is guaranteed to be clean.
2. Another advantage favoring asynchronous rets is that the circuit can be ret with or without a clock prent. Disadvantages of asynchronous rets
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1. The Reu Methodology Manual(RMM) syggests that asynchronous rets are not be ud becau they cannot be ud with cycle bad simulators.世博展馆
2. For DFT, if the asynchronous ret is not directly driven from an I/O pin, then the ret net from the ret driver must be disabled for DFT scanning and testing. This is required for the synchronizer circuit.
3. The beggest problem with asynchronous rets is that they are asynchronous, both at the asrtion and at the de-asrtion of the ret. The asrtion is a non issue, the de-asrtion is the is
sue. If the asynchronous ret is relead at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the ret state of the ASIC could be lost.
4. Another problem that an asynchronous ret can have, depending on its source, is spurious rets due to noi or glitches on the board or system ret.
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