CMOS Technology Characterization for Analog and RF Design
Behzad Razavi,Member,IEEE
Abstract—The design of analog and radio-frequency(RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer process and emerging circuit applications.The sophisticated t of characteristics ud to reprent today’s“digital”technologies often proves inadequate for analog and RF design,mandating many additional measurements and iterations to arrive at an acceptable solution.This paper describes a t of characterization vehicles that can be employed to quantify the analog behavior of active and passive devices in CMOS process,in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noi,linearity,loss,matching,and dc characteristics.
Index Terms—Analog circuits,device noi,mismatch,MOS devices,RF circuits,technology characterization.
I.I NTRODUCTION
A S CMOS technology continues to benefit from both
2014高考志愿填报时间scaling and the enormous momentum of the digital market,many high-speed and radio-frequency(RF)integrated circuits that were once considered the exclusive domain of III–V or silicon bipolar technologies are likely to appear as CMOS implementations.However,issues such as technology development costs,computer-aided design(CAD)infrastruc-ture,and fabrication turnaround time make it desirable to u a single mainstream digital CMOS process for all IC products.“Analog process”may be approaching extinction.
The design of analog and RF circuits in a digital CMOS technology faces many difficulties:the t of available active and passive devices is quite limited,the technology is opti-mized for digital design,and the devices are characterized and modeled according to simple benchmarks such as current drive and gate delay.While thefirst two issues can be somewhat alleviated by circuit and architecture innovations,the quandary of poor characterization leads to substantial conrvatism in analog design,thus resulting in circuits that do not exploit the“raw”speed of the technology.In some cas,even conrvatism does not solve the problem,mandating lengthy iterations in the design.For example,in a narrow-band RF oscillator,it is difficult to guarantee a correct output frequency without accurate data on device parasitics and their variation with process and temperature.
This paper describes a t of technology characterization methods that provide the basic information
required in ana-
Manuscript received August11,1998;revid October26,1998.
The author is with the Electrical Engineering Department,University of California,Los Angeles,CA90095USA.
Publisher Item Identifier S
0018-9200(99)01651-0.
Fig.1.Analog design octagon.
log and RF design.It also reviews some relevant modelingonlinejudge
althoughdifficulties.Section II prents the motivation for and the
issues related to the task.Sections III and IV deal with
characterization for analog and RF design,respectively.For
the sake of brevity,we u the term“analog”to mean“analog
and RF.”
II.M OTIV ATION AND I SSUES
The principal difficulty in using a digital CMOS technol-
ogy for analog design is that the process is optimized and
characterized for primarily one tradeoff:that between speed
and power dissipation.By contrast,analog circuits entail a
multidimensional design space.This is illustrated in Fig.1,
where almost every two parameters trade with each other.The
true verity of the tradeoffs is known only if relevant data
have been obtained for the technology.
The need for specialized“analog characterization”aris
from two types of shortcomings:inaccurate ,the
output resistance of transistors or its nonlinearity)or simply
lack of ,lf-resonance frequency of inductors
or matching properties of transistors).While efforts toward
improving submicrometer device models continue vigorously,
scaling appears to degrade the modeling accuracy faster.That
is,it ems that for no generation of CMOS devices have
models been sufficiently accurate.1
It is also important to note the rapid migration of digital
circuits from one generation of the technology to the next.
Analog circuits have historically lagged behind by more than
one generation,failing to utilize the full potential of new
process or to comply with their supply-voltage scaling.A
solid understanding of the properties and limitations of devices
1This is the author’s opinion rather than a documented fact.
0018–9200/99$10.00©1999IEEE
clamped
also minimizes the number of design iterations and hence the time to market.
The above obrvations indicate that analog design in a new technology can be greatly simplified if measured data points describing the analog behavior of devices and subcircuits are obtained.In fact,such data points do become available as analog designers begin to u a process,but in an ad hoc manner and very slowly.A unified effort to collect all of the necessary data soon after the qualification of a technology is rarely en.
Technology characterization for analog design nonetheless involves a number of difficult issues.
•Owing to the lack of universally applicable analog bench-marks,many test structures must be built to satisfy the needs of various systems.Op-amps,filters,comparators, data converters,oscillators,pha-locked loops,frequency synthesizers,and RF transceivers incorporate many dif-ferent functions that heavily depend on poorly modeled properties of devices.
•Some device characteristics,for example,capacitor mis-
match and thermal
and
characterization eks to minimize the
overall error in the curvefitting procedure,thus incurring
significant relative local errors.While advanced models such
as BSIM3v3incorporate many parameters to lower such errors,
some submicrometer device properties still defy accurate rep-
美国大选第二场辩论直播rentation.For this reason,it is important to have measured
I–V data points in a range suitable to analog design,
<,
mV
and
A/
in-
creas.In fact,time-domain simulation of circuits in which
MOSFET’s reciprocate between the two regions exhibit sub-
stantial dynamic errors.For example,in two-tone simulations
of RF CMOS circuits,the output spectrum often suffers from
a high noifloor that is an artifact of slope discontinuities in
the device equations.This issue remains unresolved in most
mainstream models.
Subthreshold operation actually proves uful in some cas.
For example,as depicted in Fig.2,a diode-connected MOS-
FET biad in subthreshold exhibits a large incremental resis-
tance,thus creating a low cutoff frequency in the high-pass
filter formed
with
Fig.3.Measured variation of MOS output resistance versus V DS:
Fig.4.Capacitance–voltage characteristic of an MOS device along with its derivative.
also uful to obtain measured plots of
mV and A/
–
Fig.8.Simple comparator for measuring metastability.
topologies.The speed of the circuits and its correlation with
process corner models constitute a more reliable basis for
design than tho of ring oscillators using simple inverters.
Another circuit that exercis the intrinsic speed of the
only girl (in the world)
technology is a voltage comparator.Fig.8shows an example
where
and
does not change the regeneration time constant.
C.Linearity
The linearity of both passive and active devices plays a
critical role in many analog circuits.The value of a resistor
or a capacitor can be expresd in terms of the voltage across
the device as
domestic
or node
,and the other is connected to ground,thus establishing
the value of mismatch
resistor–capacitor network prevents oscillations due to large
parasitic inductances in the tup.
It is also desirable to include nominally identical current
sources[Fig.11(b)].Since the mismatch between two current
sources depends on both the threshold voltage mismatch
and mismatch[11],[6],measurements on both
validity of the extracted data.
Measurement of resistor mismatch usually requires a four-
point(“force”and“n”)arrangement so as to avoid resis-
Fig.9.(a)Sources of nonlinearity in a folded-cascode op-amp,(b)measurement of input nonlinearity,and (c)measurement of output nonlinearity.(Common-mode feedback not
shown.)
Fig.10.Arrangement for measuring op-amp distortion.
portsmouthtance mismatches due to external connections.The topology shown in Fig.12allows such a measurement with a relatively small number of pads.
Characterization of capacitor matching is quite difficult.For small capacitors ud in most analog circuits,in the range of 0.1–1pF,direct measurement would suffer from many uncertainties resulting fr
om parasitics in the physical tup.Thus,the capacitors must be isolated from external connections by means of on-chip circuitry.Fig.13illustrates an efficient approach to measuring capacitor mismatch [12].
The top plates
of
,and a PMOS source follower rves as a buffer.The n-well
of
whileenly
and
this approach cancels
the effect of three nonidealities:1)the initial charge at
node
,including the input
pba
