Spring Semester, 2008
PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 9)
Woogeun Rhee Institute of Microelectronics Tsinghua University
HW #3
教师代表讲话• Design PFD and Charge Pump: - Goal: Determine the minimum pul width ΔtDLY to avoid dead-zone. -- Show U, D, IU, ID, and IU – ID waveforms for 2 cycle slipping periods. -- First run w/o DLY and then run w/t DLY to demonstrate dead-zone effect. - Simplest functional design is ok. No high performance is necessary. -- U of ideal gates is acceptable for PFD. -- Simple single-ended charge pump design is ok. - Due date: May 20th
VDD
DQ
10MHz
U
ΔtDLY?
A
小学生必背古诗70首VDD
CLR
tower craneICP
DLY DQ第69届金球奖
9.98MHz
D
hattrick1μF (t Vinit = 1V)
bragging rightsB
打电话英文怎么说
CLR
2
W. Rhee, Institute of Microelectronics, Tsinghua University
Circuit Design – VCO
Deadzone Speed Differential? … Mismatch Vout compliance Noi Linearity Differential? Programmable? … On-chip? Leakage Area Coupling MIM cap? Differential? … LC or ring? Tuning range Noi PSRR Power Differential? …
fref
PFD
arbor dayCP
LPF
VCO查询四级准考证号
fout
/N
Speed Power Noi Differential? …
3
handsome boyW. Rhee, Institute of Microelectronics, Tsinghua University
VCO Design Considerations
• Architecture - LC or ring? - Differential or single-ended? • Tuning Range - Fundamental trade-off between tuning range and noi - Input control voltage range and CP output voltage compliance • Noi - Random noi - VCO gain, Q, … - Deterministic noi - PSRR, substrate noi coupling, … • Power consumption - LC for high frequency • Output amplitude - Check driving capability for frequency divider. • Oscillation condition - Carefully check over PVT variations
4
W. Rhee, Institute of Microelectronics, Tsinghua University
Oscillator and VCO
Pha Noi (Small Signal) Tuning Range (Large Signal)
KVCO
fo
fo
• Fundamental tradeoff between noi and tuning range. • Best oscillator design does not necessarily guarantee best VCO!!
5
W. Rhee, Institute of Microelectronics, Tsinghua University
