A Capacitor-Free CMOS Low-Dropout Regulator
With Damping-Factor-Control Frequency
laborintensiveCompensation
Ka Nang Leung,Member,IEEE,and Philip K.T.Mok,Senior Member,IEEE Abstract—A1.5-V100-mA capacitor-free CMOS low-dropout
regulator(LDO)for system-on-chip applications to reduce board
space and external pins is prented.By utilizing damping-factor-
control frequency compensation on the advanced LDO structure,
英文在线the propod LDO provides high stability,as well as fast line and
抱怨英文load transient respons,even in capacitor-free operation.The pro-
pod LDO has been implemented in a commercial0.6-
Fig.1.Structure of classical LDO.
pMOS transistor operating in saturation region,a feedback-re-sistor network,and a voltage reference.The structure is intrinsi-cally unstable becau it has three low-frequency poles,which are generated at the outputs of LDO,the voltage buffer,and the error amplifier,respectively.Dominant-pole compensation with pole-zero cancellation scheme,which is achieved by the off-chip capacitor and its equivalent ries resistance (ESR),is utilized for LDO stability [1]–[4],[7].In addition,the design of high-output-swing voltage buffer is critical to low-voltage LDO design.Often,the voltage buffer is a source follower,which cannot provide a high output swing to fully turn on (for pMOS-implemented source follower)or off (for nMOS-implemented source follower)the power transistor in low-voltage supply ef-ficiently.Approaches using depletion MOS transistor [4]and bipolar junction transistor (BJT)[1]cannot be realized in stan-dard CMOS technologies.
The stability of classical LDOs bad on dominant-pole com-pensation with pole-zero cancellation can be studied in Fig.2.
The cond
pole
created by the ESR of the output capacitor.With a large output capacitance,the LDO stability is achieved by
locating
(1)
Load
Regulation
are the transconductance and output resistance
of the power pMOS transistor,respectively.From the above equations,a high loop gain is required for a high-precision LDO output voltage,but the LDO stability is sacrificed when loop gain is too high.Thus,there is always tradeoff between preci-sion and stability.
Load transient respon is critical when there is a sudden change in load current,and a good load tra
nsient respon results in minimal overshoot,as well as undershoot,and fast recovery time.In fact,the respon time of an LDO,which depends on the slew rate at the gate drive of the power transistor and the loop-gain bandwidth,can be improved by a high slew-rate voltage buffer and advanced frequency compensation technique.Yet,more static power consumption is required,and dominant-pole compensation cannot effectively provide a wide loop-gain bandwidth.
PSRR depends highly on both loop-gain bandwidth and ESR.An LDO with a good PSRR and line transient respon results in a good ripple rejection ratio,which is vital for an LDO as a post-regulator of switching-mode power converter.commentaries
LEUNG AND MOK:CAPACITOR-FREE CMOS LOW-DROPOUT REGULATOR
1693
Fig.3.Structure of the propod LDO with capacitor-free feature.
From the above discussions on classical LDO using domi-nant-pole compensation,a high loop gain and a wide loop band-width are critical for the improvement of LDO performance,but static power consumption and stability are tradeoffs.It is further illustrated that classical LDOs cannot be applied effectively to system-on-chip designs due to the required large output capac-itor for stability.Therefore,an advanced LDO structure with advanced frequency compensation,which solves the tradeoff problems of classical LDOs,is prented in next ction.
III.A DV ANCED LDO S TRUCTURE W ITH
D AMPING-F ACTOR-C ONTROL C OMPENSATION
From the previous discussion,the classical LDO suffers from a stability problem.This problem is due to the low-frequency poles,and hence,large off-chip capacitance and ESR are needed for clod-loop stability.In fact,this problem can be solved by pole splitting.However,classical two-stage-amplifier topology is not optimum since the power transistor cannot function as a high-gain stage in d
ropout condition.The pole-splitting effect is thus not effective and the output precision is also degraded. Instead,an LDO can be viewed as a three-stage amplifier with the power transistor as the last stage.When using this approach, as will be discusd later,the positions of the nondominant poles depend on the transconductance of the power transistor and the output capacitance.The larger transconductance and smaller output capacitance results in higher frequencies of the nondominant poles.Therefore,the worst ca stability occurs at zero load-current condition as the transconductance is minimum(about5–10mA/V,typically)when only a current
equaled
to A drains from the
power transistor.Advanced frequency compensation tech-niques are required to generate a more effective pole-splitting effect incorporated with pole-zero cancellation.The pushed nondominant poles can be cancelled more effectively by extra zeros at higher frequencies.The required passive components to generate the zeros can be much smaller,and the coupling noi is,hence,reduced significantly.A stable and fast-respon LDO can,therefore,be achieved.In this ction,the novel LDO with DFC frequency compensation bad on this novel idea is discusd.
The structure of the propod LDO with DFC frequency compensation and a first-order high-pass feedback network is shown in Fig.3.It is compod of a high-gain error amplifier, a high-gain high-output-swing cond stage,a power pMOS transistor operating in linear region at dropout,a feedback resistive network with first-order high-pass characteristic,a CMOS voltage reference,and a DFC block with compensation
capacitors
)are created,
and are,respectively,given
by
(4)
1694IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.38,NO.10,OCTOBER
2003
delay什么意思
Fig.4.Complete schematic of the propod
LDO.
Fig.5.Feedback-resistive network with first-order high-pass characteristic.
The zero frequency is lower than the pole frequency,and this zero,as will be discusd later,can be ud to cancel the effect of nondominant poles created in the propod LDO.In order to
have
日不落英文
and
,the transconduc-
tance
of the power pMOS is at the minimum and maximum,respectively.This is the worst ca stability of the propod compensation scheme.In this sit-uation,the DFC scheme provides a transfer function,which is given
by
and
,
and
A for low-power
LDO designs.
Therefore,
sut
在线翻译英译汉
LEUNG AND MOK:CAPACITOR-FREE CMOS LOW-DROPOUT REGULATOR
1695
(a)
(b)
(c)
Fig.6.Loop gain (magnitude plot only and not in scale)of the propod LDO structure.(a)
C =0and
I
=0.(b)
C
=0and
I
=0.
(c)
C =0and
I =0.
We compare the cond-order function in (7)with a standard cond-order function given
by
is the damping factor
and
demonand
履历表格式
to make the system stable.As a remark,the low-frequency loop gain decreas
and
.B.Stability Without Off-Chip Capacitor
When the propod LDO is ud in system-on-chip designs without an off-chip capacitor,the LDO is also stable.There is a minimum load current (about 100
