micron

1GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

GENERALDDRSDRAM

FUNCTIONALITY

INTRODUCTION

Themigrationfromsingledataratesynchronous

DRAM(SDR)todoubledataratesynchronousDRAM

(DDR)ghtherearemany

similarities,DDRtechnologyalsoprovidesnotable

productenhancements.

Ingeneral,doubledataratememoryprovides

source-synchronousdatacaptureatarateoftwicethe

ore,aDDR266devicewitha

clockfrequencyof133MHzhasapeakdatatransfer

rateof266Mb/sor2.1GB/

accomplishedbyutilizinga2n-prefetcharchitecture

wheretheinternaldatabusistwicethewidthofthe

externaldatabusanddatacaptureoccurstwiceper

idehigh-speedsignalintegrity,the

DDRSDRAMutilizesabidirectionaldatastrobe,

SSTL_2interfacewithdifferentialinputsandclocks.

Theobjectiveofthistechnicalnoteistoprovidean

overviewofthe2n-prefetcharchitecture,astrobe-bad

databus,andtheSSTL_2interfaceudwithDDR

alsohighlightthefunctionaldifferences

betweenSDRandtheimprovedDDRmemorytechnol-

aileddesignandtimingcriteriaforDDR

SDRAM-badsystems,eMicron'sDDRSDRAMdata

sheets.(/ddrsdram.)

Table1

SDRtoDDRQuickReference

TableofContents

ctionality...............................2

Table1:SDRtoDDRQuickReference.................1

Figure1:FunctionalBlockDiagram....................2

Figure4:ExampleofDDRCommandBus..........3

2n-PrefetchArchitecture.................................3

Figure2:BlockDiagram2n-PrefetchREAD........3

Figure3:BlockDiagram2n-PrefetchWRITE.......3

MinimumTimeSlots........................................3

Figure5:2n-PrefetchREADSlotTiming.............4

Figure6:2n-PrefetchWRITESlotTiming............5

Figure7:READCommandSlots...........................6

Strobe-BadDataBus.....................................4

PreambleandPostamble.................................7

Figure8:DQSREADPostambleandPreamble...7

Figure9:DQSWRITEPostambleandPreamble.8

SSTL_2Interface...............................................9

DriversandReceivers......................................9

Figure10:TypicalLVCMOSReceiver...................9

Figure11:TypicalSSTL_2Receiver......................9

I/OSignaling....................................................10

Figure12:TypicalSSTL_2Interfaceand

nputLevels.......................................10

ClockInputs.....................................................11

Figure13:SSTL_2Clocks.....................................11

Summary.........................................................11

PARAMETERSDRDDRNOTES

DQMYesNoUdforwritedatamaskandreadOE

DM(DataMask)NoYesReplacesDQM,udtomaskwritedataonly

DQS(DataStrobe)NoYesNew,udtocapturedata

CK#(SystemClock)NoYesNew,DDRutilizesdifferentialclocks

VREFNoYesReferencevoltagefordifferentialinputs(1/2VDD)

VDDandVDDQ3.3Volts2.5VoltsReducedsupplyandpowerforDDR

SignalInterfaceLVTTLSSTL_2DDRutilizesdifferentialI/O

OutputDriveFixedVariablex16DDRdevicesofferareduceddriveoption

DataRate1xClock2xClockDatatransferistwicetheclockrateforDDR

ArchitectureSynchronousSource-SynchronousDDRutilizesabidirectionaldatastrobe

TECHNICAL

NOTE

2GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

12

RAS

#CAS

#ROW-

ADDRESS

MUX

CK

CS

#WE

#CK

#CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODEREGISTERS

11

C

O

M

M

A

N

D

D

E

C

O

D

E

A0-A11,

BA0,BA1

CKE

12

ADDRESS

REGISTER

14

1,024

(x8)

4,096

I/OGATING

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096x1,024x8)

BANK0

ROW-

ADDRESS

LATCH

AND

DECODER

4,096

SENSEAMPLIFIERS

BANK

CONTROL

LOGIC

12

BANK1

BANK2

BANK3

12

1

2

2

REFRESH

COUNTER

-

DQM

DQ0-

DQ3

4

4

4

4

DATA

INPUT

REGISTER

DATA

OUTPUT

REGISTER

11

InternalDataBus

x4forSDR

x8forDDR

InternalDataBus

InternalDataBus

(SDR)

DQM

DQM

NotUdforDDR

(DDR)

DDRI/OInterface

SDRI/OInterface

GenericMemoryArray

NotUdforSDR

Figure1

FunctionalBlockDiagram

2Megx4MemoryArraywithSDRandDDRInterface

CTIONALITY

SDRSDRAMiswellestablishedandgenerallyun-

derstood,soquestionstendtofocuswhereDDRdif-

fersfromSDR.

Anexaminationofthe32Megx4SDRandDDR

functionalblockdiagramsrevealsthatthememorycore

isntiallythesame(eFigure1).Bothhavean

identicaladdressingandcommandcontrolinterface;

bothhaveafour-bankmemoryarray;andbothincor-

damen-

taldifferencesarefoundinthedatainterface.

TheSDRmemorydatainterfaceisafullysynchro-

nousdesignwherethedataisonlycapturedonthe

ernalbusisthesamewidth

astheexternaldatabusanddatalatchesintotheinter-

nalmemoryarrayquentiallyasitpassthroughthe

I/oryalsosupportsaDQMsignal

thatactsasadatamaskduringaWRITEoperationor

anoutputenableforaREAD.

TheDDRmemorydataisatruesource-synchro-

nousdesign,wherethedataiscapturedtwiceperclock

chitecture

employsa2n-prefetcharchitecture,wheretheinter-

allowstheinternalmemorycelltopassdatatotheI/O

R,thereisnooutputenable

forREADoperations,butDDRdoessupportaBURST

TERMINATEcommandtoquicklyendaREADinpro-

aWRITEoperation,theDMsignalisavail-

abletoallowthemaskingofnonvalidwritedata.

TheDDRcommandbusconsistsofaclockenable,

chiplect,rowandcolumnaddress,bankaddress,

dsare

enteredonthepositiveedgesofclock,anddataoccurs

onbothpositiveandnegativeedgesoftheclock.

Thedoubledataratememoryutilizesadifferential

pairforthesystemclockandthereforewillhavebotha

trueclock(CK)andcomplementaryclock(CK#)signal.

ThepositiveclockedgeforDDRreferstothepoint

wheretherisingclocksignalcrosswiththefalling

complementaryclocksignal,andthetermnegative

clockedgeindicatesthetransitionofthefallingclock

andrisingcomplementaryclocksignals.

3GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

n

-bit

Data

Register

n

-bit

Data

Register

CLKD

n

-bitdata

plusDQS

Q

D0

MUX

D1

C

DQS

From

DRAM

Core

2

n

-bit

data

n

-bit

data

n

-bit

data

AllDQ

andDQS

Outputs

DQS

Figure2

SimplifiedBlockDiagram

of2n-PrefetchREAD

CS

#WE

#CAS

#RAS

#CKE

CA

A10

BA0,1

HIGH

ENAP

DISAP

BA

CK

CK

#CA=ColumnAddress

RA=RowAddress

Ai=MostSignificantAddress

BA=BankAddress

ENAP=EnableAutoPrecharge

DISAP=DisableAutoPrecharge

DON’TCARE

A0–Ai

A0–AiRA

CK

2

n

-bit

data

DQ0-DQi

n-bit

data

n

-bit

data

To

DRAM

Core

n

-bit

Data

Register

D

Q

n

-bit

Data

Register

DQ

2

n

-bit

Data

Register

DQ

DQS

Figure4

ExampleoftheDDRCommandBus

foraWRITECycle

2n-PrefetchArchitecture

ThetermDDR(orDDRI)shouldbespecificallyas-

sociatedwiththe2n-prefetchdevice,asfuturememory

designs(DDRII)willuthe4n-prefetcharchitecture.

TotheDRAMvendor,2n-prefetchmeansthatthe

internaldatabuscanbetwicethewidthoftheexternal

databus,andthereforetheinternalcolumnaccess

frequencycanbehalfoftheexternaldatatransferrate.

Thatis,foreachsinglereadaccesscycleinternaltothe

device,twoexternaldatawordsareprovided(asshown

inFigure2).Similarly,twoexternaldatawordswritten

tothedeviceareinternallycombinedandwrittenin

oneinternalaccess(asshowninFigure3).

Totheur,fromahigh-levelview,2n-prefetch

meansthatdataaccessoccurinpairs;i.e.,asingle

readaccessfetchestwodatawords;andforasingle

writeaccess,twodatawords(and/ordatamaskbits)

fectsboththeminimumburst

i-

mumburstsizeofa2n-prefetcharchitectureistwo

externaldatatransfers.

MinimumTimeSlots

ForREADs,thecontrollercanchootoignoreei-

therofthetwowords,butthetimeslotsforbothwillbe

occupied(eFigure5).Similarly,forWRITEs,thecon-

trollercanmaskeitherofthetwowords,butagain,the

timeslotsareoccupied(eFigure6).ForeachREADor

WRITEcommand(andcolumnaddress)applied,two

ethedeviceisdouble

datarateaswellas2n-prefetch,aminimumoftwodata

wordsisoptimal(sincecommandscannotbeapplied

morefrequently).

Figure3

SimplifiedBlockDiagramof

2n-PrefetchWRITE

4GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

CK

CK

#COMMAND

NOPREADREAD

ADDRESS

NOP

Bank,

Coln

READ

Bank,

Colx

Bank,

Colb

READ

Bank,

Colg

DQ

DQS

CL=2

DON’TCARE(toDRAM)

DON'TCARE(tocontroller)

NOTES:,etc.=data-outfromcolumnn,etc.

2.n',etc.=thenextdata-outfollowingDOn,etc.,

accordingtotheprogrammedburstorder.

ength=2,4,or8incasshown.

retoactiverowsinanybanks.

ithnominal

t

ACand

t

DQSQ.

trollerwantsthefirstoftwowordsforthefirst

READcommand,bothwordsforthecond,andthe

condoftwowordsforthethird.

DO

n

DO

x'

DO

b'

DO

g

DO

b

DO

x

DO

n'

Figure5

MinimumDataTimeSlotfor2n-PrefetchREAD

Strobe-BadDataBus

Inapurelysynchronoussystem,dataoutputand

capturearereferencedtoacommon,free-runningsys-

r,themaximumdatarateforsucha

systemisreachedwhenthesumofoutputaccesstime

andflighttimeapproachesthebittime(thereciprocal

ofthedatarate).Althoughgeneratingdelayedclocks

forearlydatalaunchand/orlatedatacapturewillallow

forincreaddatarate,thetechniquesdonotac-

countforthefactthatthedatavalidwindow(ordata

eye)movesrelativetoanyfixedclocksignal,dueto

changesintemperature,voltage,,toal-

lowforevenhigherdatarates,datastrobesignalswere

astrobesarenonfree-

runningsignalsdrivenbythedevice,whichisdriving

thedatasignals(thecontrollerforWRITEs,theDRAMs

forREADs).AttheDRAMdevicelevel,forREADs,the

datastrobe(DQS)signalsareeffectivelyadditional

dataoutputs(DQ)withapredeterminedpattern;for

WRITEs,thestrobesignalsareudasclockstocap-

oardlevel,

thestrobesignalshaveidenticalloadingtodatasig-

nalsandshouldberoutedsimilarly.

FornonminimumREADbursts(fouroreightwords),

ithelpstoassociateeachpositiveclockedgewithapair

y,interruptionsofREADcom-

mple,withaburst

lengthofeight,aREADcommandfollowedbythree

uninterruptingcommandsisneededtoaccesstheen-

terruptingcommandisappliedatthe

firstpositiveclockedgefollowingtheREADcommand,

onlytwowordswillbeaccesd;ifaninterruptingcom-

mandisappliedatthecondpositiveclockedgefol-

lowingtheREADcommand,onlyfourwordswillbe

accesd,etc.,(eFigure7).

Theconceptofassociatingpairsofdatawithposi-

r,to

fullyunderstandthemaskingandinterruptingofwrite

data,WRITElatencyandstrobe-baddatabustim-

itshouldbenoted

thatthepositiveclockedgesofinterestforWRITEsare

becauofdif-

ferencesinlatenciesandbecauthearrayaccessoc-

cursatthebeginningofaREADoperationbutatthe

,therelevantedges

dependonwhattheinterruptingcommandis,aswe

willbeshownlater.

5GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

Figure6

MinimumDataTimeSlotfor2n-PrefetchWRITE

t

DQSS(NOM)

CK

CK

#COMMAND

WRITEWRITEWRITEWRITE

ADDRESS

Bank,

Colb

Bank,

Colx

Bank,

Coln

Bank,

Colg

WRITE

Bank,

Cola

NOTE:,etc.=data-inforcolumnb,etc.

2.b',etc.=thenextdata-infollowingDIb,etc.,accordingtotheprogrammedburstorder.

mmedburstlength=2,4,or8incasshown.

ITEcommandmaybetoanybank.

5.

ThecontrollerwantstowritethefirstoftwowordsforthefirstWRITEcommand,

bothwordsforthecond,andthecondoftwowordsforthethird.

DQ

DQS

DM

DI

b

DI

x

DI

x'

DI

n'

DI

a

DI

a'

DON’TCARE(toDRAM)

Atthispoint,itmaybehelpfultodigressforamo-

technicalnotefocusontypicaldesktopPCmain

memoryapplications,whichux64DIMMscon-

llersfor

theapplicationswillbedesignedwithonestrobeper

byte;i.e.,thereisonestrobeoneachx8DRAMdevice

andtwostrobesoneachx16device.

Othertypesofapplicationsmayudifferentstrobe-

mple,rversusingx72DIMMs

badonx4componentsrequirecontrollerswithone

strobeperfourbits,andcontrollersforgraphicsorcom-

municationsapplicationsmightuonetofourstrobes

vetechniquescanbeutilizedtomix

andmatchdifferentstrobe-to-dataratiosinasystem,

eofthefocus

ofthistechnicalnote,astrobe-to-dataratioofoneper

ingandcalculationsdescribed

applyindependentlytoeachgroupofsignals.

ForREADs,thedatastrobesignalsareedge-aligned

withthedatasignals,meaningthatalldataanddata

strobesareclockedoutofthedevicebythesameinter-

nalclocksignal,andallwilltransitionattheoutputsat

trollerwillinternally

delaythereceivedstrobetothecenterofthereceived

dataeye.

ForWRITEs,thecontrollermustprovidethedata

,strobe

transitionsoccurnominally90degrees(relativetothe

clockfrequency)outofphawithdatatransitions.

TheDRAMdeviceusinternallymatchedroutingfor

thestrobesanddatasuchthatthestrobescanbeud

atthereason

READsandWRITEsuadifferentalignmentscheme

issothatthedelaycircuitrycanbecentralizedinone

place(thecontroller)anddoesnothavetoberepli-

-

proachixpectedtobecarriedforwardtofuturegen-

erationsofDDRtoleveragetheinfrastructurenowbe-

ingestablished.

6GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

Figure7

RelatingCommandSlotstoReadData

CK

(Pair1)Pair2Pair3Pair4

CK

#COMMAND

NOPNOPNOPNOPREADnNOP

CL=2

DON’TCARE

DQ

COMMAND

NOPNOPNOPREADnNOP

CL=2

DQ

COMMAND

NOPNOPNOPBSTREADnNOP

CL=2

DQ

COMMAND

NOPNOPNOPBSTREADnNOP

CL=2

DQ

NOP

NOTE:=data-outfromcolumnn.

mandsreprentanyvaliduninterruptingcommands.

mandsreprentanyvalidinterruptingcommands.

llingcommandslotsarenotedforeachpair;ifaninterruptingcommandis

appliedinthecontrollingcommandslotforagivendatawordpair,thatpairwill

notbereadout.

1isalwaysreadout(i.e.,istheminimumburst)whenaREADcommandisapplied.

BST

DO

n

DO

n

DO

n

DO

n

PAIR1PAIR2PAIR3PAIR4

7GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

Figure8

DQSPatternforREADShowingPreambleandPostamble

Preamble

Postamble

CK

T0T1T2T3T4T5T6T7T8T9T10T11

CK

#COMMANDNOPNOPNOPNOPREADnNOP

DON’TCARE

DQ

DQS

NOTE:=data-outfromcolumnn.

ength=4,CASlatency=2.

ubquentelementsofdata-outappearintheprogrammedorderfollowingDOn.

ith

t

ACand

t

DQSQ=0forillustration.

DO

n

PreambleandPostamble

Thedatastrobetimingpatternconsistsofa

preamble,toggling,8

showsthestrobepatternandalignmenttodatafor

READs,

preambleportionprovidesatimingwindowforthe

receivingdevicetoenableitsdatacapturecircuitry

whileaknown/validlevelisprentonthestrobesig-

nal,thusavoidingfaltriggersofthecapturecircuit.

Followingthepreamble,thestrobeswilltoggleatthe

samefrequencyastheclocksignalforthedurationof

ghtransitionandeachlowtran-

time

followingthelasttransitionisknownasthepostamble.

Mostcontrollershaveaninternalclockrunningattwice

thememoryclockfrequency,sogeneratingastrobe

shifted90degreesrelativetodataisfairlystraightfor-

lly,dataandstrobeareclockedoutusing

the2xclock,withdatabeingdrivenbyedgesofone

polarity,andthestrobebeingdrivenbyedgesofthe

ngtheincomingstrobefor

READsismoreinvolvedandwillbecoveredindetailin

anindependenttechnicalnote.

Forread-to-readdatabustransitionswherethe

READsarefromdifferentphysicalbanksofDRAMs,or

read-to-writedatabustransitions(i.e.,transitionsfrom

onedevicedrivingthedatabustoanotherdevicedriv-

ingthedatabus),thereisahand-offofstrobesignals,

andthefullstrobepattern(includingpreamblesand

postambles)r-

vativeapproachistospacerequestssuchthatthe

postamblefromthefirstsourcecompletesbeforethe

utive

READburstsfromthesamebankofDRAMsare

achievedbyextendingthetogglingportionofthedata

strobepattern.(Apostambleandpreamblearenot

neededbetweenconcutiveREADburstsfromthe

samesource.)ConcutiveWRITEburstsarealsopos-

sible,eveniftodifferentphysicalbanksofDRAMs.

Thisisalittlelessintuitivebecau,unlikethecaof

concutiveREADsfromthesamesource,thedestina-

tionDRAMsforthecondconcutiveWRITEburst

havenowayofknowingthatafirstWRITEburstto

ansthatthe

DRAMsmustbecapableofacceptingdifferentpre-

ambletiming,dependingonwhethertherewasprior

writeactivityonthebus.

8GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

CK

CK

#COMMAND

WRITEbNOPNOPNOP

DQ

DQS

DON’TCARE

DI

b

T0T1T2T3T4T5T6

Preamble

Postamble

NOTE:=data-inforcolumnb.

ubquentelementsofdata-in

areappliedintheprogrammedorderfollowingDIb.

offourisshown.

ithnominaltDQSSandwithoutDMbits

forillustration.

Figure9

DQSPatternforWRITEShowingPreambleandPostamble

9GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

TN4605.p65–Rev.A;Pub.7/01©2001,MicronTechnology,Inc.

TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

SSTL_2Interface

PreviousSDRmemorytechnologyudLVTTLand

AM

utilizesdifferentialinputsandareferencevoltagefor

terfaceiscalledSSTL_2,

whichstandsforstubriesterminatedlogicfor2.5

_2isanindustrystandarddefinedbyJEDEC

document#EIA/ghsomeDRAMswill

supportareduceddriveoutput,mostwillcomplywith

theSSTL_2ClassIIdrivelevels.

BenefitstotheSSTL_2interfaceincludesymmetri-

callowandhighlogiclevels,improvedsignalintegrity,

andbetternoiimmunity,astheinputlevelstrack

minorvariationsinthesupplyvoltage.

VDDQ=3.3V

OutIn

VSS

DriverandReceivers

Theoutputbufferandinputreceivershavechanged

fromLVTTLtoSSTL_putbufferlogichasnot

changed,buttheVDDQhasmovedfrom3.3voltsto2.5

voltsforDDR.

Theinputreceivershavemigratedfromannandp

channelstackedgatetoadifferentialpaircommon

ecomplexreceiverudinDDR

providesgreaterbandwidthandasmallervariation

overtemperaturetoincreamargintothetighterin-

sbeenaddedtoimproveVDD

marginovertemperature.

VDDQ=2.5V

InVREF

VSS

VOUT

Figure10

TypicalLVCMOSReceiver

Figure11

TypicalSSTL_2Receiver

10GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

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TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

I/OSignaling

ThetypicalSSTL_2interfaceincludesriestermi-

nationandapull-uptotheterminationvoltage(refer

toFigure12).TheSSTL_2interfaceusareference

voltageanddifferentialinputtodeterminethelogic

erencevoltageisdefinedtobehalfofthe

supplyvoltageandtheterminationvoltageequals

thereferencevoltage.(VDD=2.5volts,VREF=VTT=1.25

volts).

VREF

-

+

VTT

RT

RS

VIN

VOUT

Driver

Receiver

Figure12

TypicalSSTL_2InterfaceandInputLevels

TherearebothDCandACinputlogiclevelsforthe

SSTL_ral,theDRAMwillstartto

switchtothenewlogiclevelwhentheinputsignal

transitionsthroughthetargetDClevelanditwilllatch

whentheinputsignalcrossthroughthefinalAC

elogiclevelhasbeenlatched,itwill

remainlatcheduntiltheinputsignaltransitionsback

oFigure12foratypical

SSTL_2inputsignal.

VIL(AC)

VIL(DC)

VIH(DC)

VIH(AC)

VREF

DCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS

(0°C≤T

A

≤+70°C;VDD=+2.5V±0.2V,VDDQ=+2.5V±0.2V)

PARAMETER/CONDITIONSYMBOLMINMAXUNITS

I/OReferenceVoltageVREF0.49xVDDQ0.51xVDDQV

I/OTerminationVoltage(system)VTTVREF-0.04VREF+0.04V

InputHigh(Logic1)VoltageVIH(DC)VREF+0.15VDD+0.3V

InputLow(Logic0)VoltageVIL(DC)-0.3VREF-0.15V

InputHigh(Logic1)ACVoltageVIH(AC)VREF+0.310–V

InputLow(Logic0)ACVoltageVIL(AC)–VREF-0.310V

11GeneralDDRSDRAMFunctionalityMicronTechnology,Inc.,rervestherighttochangeproductsorspecificationswithoutnotice.

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TN-46-05

GENERALDDRSDRAMFUNCTIONALITY

lWay,6,Boi,ID83707-0006,Tel:208-368-3900

E-mail:prodmktg@,Internet:,CustomerCommentLine:800-932-4992

Micron,theMlogo,andtheMicronlogoaretrademarksand/orrvicemarksofMicronTechnology,Inc.

ClockInputs

Toincreaaccuracycaudbyclockjitter,adiffer-

icesuthe

midpointoftherisingclockedgetolatchdataandthus

sthecrossingpointof

CKandCK#.Usingthecrossingpointinsteadofthe

midpointhelpsnegatetheaffectsofjitterandincrea

cksudforDDRalsooperatewithina

tofparameters,whicharedefinedbyJEDEC(e

Figure13).

CK

#CK

2.80V

MaximumClockLevel

MinimumClockLevel

-0.30V

1.25V

1.45V

1.05V

VID(AC)

VID(DC)

X

VMP(DC)

VIX(DC)

X

Figure13

TypicalSSTL_2Clocks

Reference:MicronDesignLine,Volume8,Issue3(3Q99)

DesignLineisavailableathttp:/designline

SUMMARY

ThesimilaritiesbetweenSDRandDDRSDRAMpro-

videtheDRAMmanufacturercostadvantagesandas-

imilaritiesalsohelp

thedesignertobetterunderstandDDRandallowthe

mostoptimaldesigntechniquesfrompreviousdesigns

-

thoughtheaddressingschemes,layoutrequirements,

anddeviceconfigurationsaremuchthesameforDDR,

mple,

thepowerconsumptionforDDRissignificantlyless

thanforacomparableSDRdevice,yetpeaktransfer

ratescanexceed2.1GB/sforastandardx64DDRDIMM.