asrted

Table34:ConfigurationManagementInterfacePorts

PortDirectionWidthDescription

cfg_mgmt_addrI19Read/WriteAddress.

ConfigurationSpaceDword-alignedaddress

cfg_mgmt_byte_enableI4ByteEnable

ByteEnableforwritedata,wherecfg_mgmt_byte_enable[0]

correspondstocfg_mgmt_write_data[7:0]andsoon

cfg_mgmt_read_dataO32ReadDataOut

ReaddataprovidestheconfigurationoftheConfigurationand

Managementregisters

cfg_mgmt_readI1ReadEnable

-High

cfg_mgmt_read_write_doneO1Read/WriteOperationComplete

-High

cfg_mgmt_write_dataI32Writedata

WritedataisudtoconfiguretheConfigurationand

Managementregisters

cfg_mgmt_writeI1WriteEnable

-High

DescriptorBypassMode

IfinthePCIeDMATabintheVivadoIDEeitherDescriptorBypassforRead(H2C)orDescriptor

BypassforWrite(C2H)arelected,narybitcorrespondstoa

channel:1inbitpositionsmeansthecorrespondingchannel

descriptorbypassinabled.

Table35:H2C0-3DescriptorBypassPort

PortDirectionDescription

h2c_dsc_byp_

h2c_dsc_byp_readyisdeasrted,oneadditionaldescriptor

trolregister'Run'bitmustbe

asrtedbeforethechannelacceptsdescriptors.

h2c_dsc_byp_loadIWritethedescriptorprentedath2c_dsc_byp_dataintothe

channel’sdescriptorbuffer.

h2c_dsc_byp_src_addr[63:0]IDescriptorsourceaddresstobeloaded.

h2c_dsc_byp_dst_addr[63:0]IDescriptordestinationaddresstobeloaded.

h2c_dsc_byp_len[27:0]IDescriptorlengthtobeloaded.

h2c_dsc_byp_ctl[15:0]IDescriptorcontroltobeloaded.

[0]:1tostopfetchingnextdescriptor.

[1]:1tointerruptaftertheenginehas

completedthisdescriptor.

[3:2]:Rerved.

[4]:acketforAXI-Streaminterface.

[15:5]:Rerved.

Allrervedbitscanbeforcedto0s.

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Table36:C2H0-3DescriptorBypassPorts

PortDirectionDescription

c2h_dsc_byp_

c2h_dsc_byp_readyisdeasrted,oneadditionaldescriptor

trolregister'Run'bitmustbe

asrtedbeforethechannelacceptsdescriptors.

c2h_dsc_byp_loadIDescriptorprentedatc2h_dsc_byp_*isvalid.

c2h_dsc_byp_src_addr[63:0]IDescriptorsourceaddresstobeloaded.

c2h_dsc_byp_dst_addr[63:0]IDescriptordestinationaddresstobeloaded.

c2h_dsc_byp_len[27:0]IDescriptorlengthtobeloaded.

c2h_dsc_byp_ctl[15:0]IDescriptorcontroltobeloaded.

[0]:1tostopfetchingnextdescriptor.

[1]:1tointerruptaftertheenginehas

completedthisdescriptor.

[3:2]:Rerved.

[4]:acketforAXI-Streaminterface.

[15:5]:Rerved.

Allrervedbitscanbeforcedto0s.

Thefollowingtimingdiagramshowshowtoinputthedescriptorindescriptorbypassmode.

Whendsc_byp_readyisasrted,anewdescriptorcanbepushedinwiththe

dsc_byp_loadsignal.

Figure8:TimingDiagramforDescriptorBypassMode

IMPORTANT!Immediatelyafterdsc_byp_readyisdeasrted,onemoredescriptorcanbepushedin.

Intheabovetimingdiagram,adescriptorispushedinwhendsc_byp_readyisdeasrted.

RelatedInformation

PCIeDMATab

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Spartan-3FPGAFamily:IntroductionandOrderingInformation

DS099(v3.1)June27,2013

ProductSpecification

Spartan-3FPGAFamily:IntroductionandOrderingInformation

DS099(v3.1)June27,2013

ProductSpecification

RegisterSpace

Note:Bridgemode,etheAXIBridgefor

PCIExpressGen3SubsystemProductGuide(PG194).

ConfigurationandstatusregistersinternaltotheDMA/BridgeSubsystemforPCIExpress®and

thointheurlogiccanbeaccesdfromthehostthroughmappingthereadorwriterequest

toaBaAddressRegister(BAR).BadontheBARhit,therequestisroutedtotheappropriate

eBARassignments,eTargetBridge.

PCIetoAXIBridgeMasterAddressMap

TransactionsthathitthePCIetoAXIBridgeMasterareroutedtotheAXI4MemoryMappedur

interface.

PCIetoDMAAddressMap

TransactionsthathitthePCIetoDMAspaceareroutedtotheDMASubsystemforthe

PCIeDMA/BridgeSubsystemforPCIExpress®s

supports32bitsofaddressspaceand32-bitreadandwriterequests.

DMA/BridgeSubsystemforPCIeregisterscanbeaccesdfromthehostorfromtheAXISlave

egistersshouldbeudforprogrammingtheDMAandcheckingstatus.

PCIetoDMAAddressFormat

Table37:PCIetoDMAAddressFormat

31:1615:1211:87:0

RervedTargetChannelByteOfft

Table38:PCIetoDMAAddressFieldDescriptions

BitIndexFieldDescription

15:12Target

ThedestinationsubmodulewithintheDMA

4’h0:H2CChannels

4’h1:C2HChannels

4’h2:IRQBlock

4’h3:Config

4’h4:H2CSGDMA

4’h5:C2HSGDMA

4’h6:SGDMACommon

4'h8:MSI-X

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