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Dual16-Bit,1.0GSPS

D/AConverter

PreliminaryTechnicalDataAD9779

FEATURES

•1.8/3.3VSingleSupplyOperation

•Lowpower:950mW(IOUTFS=20mA;fDAC=1GSPS,4×

Interpolation

•DNL=±1.5LSB,INL=±5.0LSB

•SFDR=82dBctofOUT=100MHz

•ACLR=87dBc@80MHzIF

•CMOSdatainterfacewithAutotrackingInputTiming

•AnalogOutput:Adjustable10-30mA(RL=25Ωto50Ω)

•100-leadExpodPaddleTQFPPackage

•MultipleChipSynchronizationInterface

•84dBDigitalInterpolationFilterStopbandAttenuation

•DigitalInverSincFilter

APPLICATIONS

•WirelessInfrastructure

DirectConversion

TransmitDiversity

•WidebandCommunicationsSystems:

Point-to-PointWireless,LMDS

PRODUCTDESCRIPTION

TheAD9779isadual16-bithighperformance,highfrequency

DACthatprovidesasamplerateof1GSPS,permittingmulti

udesfeatures

optimizedfordirectconversiontransmitapplications,including

DACoutputsareoptimizedtointerfaceamlesslywithanalog

lperipheral

interface(SPI)providesforprogrammingmanyinternal

outputcurrentcanbeprogrammedoverarangeof10mAto30mA.

TheAD9779ismanufacturedonanadvanced0.18µmCMOS

processandoperatesfrom1.8Vand3.3Vsuppliesforatotalpower

ppliedina100-leadQFPpackage.

PRODUCTHIGHLIGHTS

Ultra-lownoiandIntermodulationDistortion(IMD)enable

highqualitysynthesisofwidebandsignalsfrombabandtohigh

intermediatefrequencies.

Single-endedCMOSinterfacesupportsamaximuminputrateof

300MSPSwith1xinterpolation.

ManufacturedonaCMOSprocess,theAD9779usaproprietary

switchingtechniquethatenhancesdynamicperformance.

ThecurrentoutputsoftheAD9779canbeeasilyconfiguredfor

varioussingle-endedordifferentialcircuittopologies.

FUNCTIONALBLOCKDIAGRAM

Complex

Modulator

ClockGeneration/Distribution

2X

n*Fdac/8

n=1,2,3…7

P2D[15:0]

IOUT2_P

IOUT2_N

CLK+

CLK-

DATACLK_OUT

2X2X

2X2X2X

Sinc-1

Sinc-1

16-Bit

IDAC

16-Bit

QDAC

DigitalController

Clock

Multiplier

2X/4X/8X

Gain

Gain

Offt

Offt

Reference

&Bias

10

10

10

10

Power-On

Ret

Serial

Peripheral

Interface

QLatch

ILatch

DelayLine

DelayLine

Data

Asmbler

S

DI

O

S

D

O

S

C

L

K

C

S

B

IOUT1_P

IOUT1_N

VREF

RSET

AUX1_P

AUX1_N

AUX2_P

AUX2_N

P1D[15:0]

SYNC_I

SYNC_O

Figure1FunctionalBlockDiagram

元器件交易网

AD9779PreliminaryTechnicalData

|Page2of34

TABLEOFCONTENTS

Specifications............................................................................................3

DCSPECIFICATIONS......................................................................3

DIGITALSPECIFICATIONS............................................................4

ACSPECIFICATIONS.......................................................................4

PinFunctionDescriptions.....................................................................5

PinConfiguration....................................................................................6

InterpolationFilterCoefficients............................................................7

INTERPOLATIONFilterRESPONSECURVES................................8

CHARACTERIZATIONDATA............................................................9

GeneralDescription..............................................................................12

SerialPeripheralInterface................................................................12

GeneralOperationoftheSerialInterface......................................12

InstructionByte.................................................................................12

SerialInterfacePortPinDescriptions............................................12

MSB/LSBTransfers...........................................................................13

NotesonSerialPortOperation.......................................................13

SPIRegisterMap...............................................................................14

InternalReference/FullScaleCurrentGeneration.......................22

AuxiliaryDACs..................................................................................22

PowerDownandSleepModes........................................................22

InternalPLLClockMultiplier/ClockDistribution.....................23

TimingInformation..........................................................................23

InterpolationFilterArchitecture.....................................................25

EvaLuationBoardSchematics..............................................................27

REVISIONHISTORY

RevisionPrA:InitialVersion

RevisionPrB:UpdatedPage1Features,addedevalboardschematics,SPIregistermap,filtercoefficientsandfilterresponcurves

RevisionPrC:Addedcharacterizationdata,descriptionofmodulationmodes,internalclockdistributionarchitecture,timinginformation

RevisionPrD:Addedmoreaccharacterizationdata,powerdissipation

元器件交易网

PreliminaryTechnicalDataAD9779

|Page3of34

SPECIFICATIONS1

DCSPECIFICATIONS

(VDD33=3.3V,VDD18=1.8V,MAXIMUMSAMPLERATE,UNLESSOTHERWISENOTED)

ParameterTempTestLevelMinTypMaxUnit

RESOLUTION16Bits

IntegralNonlinearity(DNL)

±1.5

LSB

ACCURACY

DifferentialNonlinearity(INL)

±5

LSB

OfftError

±TBD

%

F

SR

GainError(WithInternalReference)

±TBD

%

F

SR

GainError(WithoutInternalReference)

±TBD

%

F

SR

FullScaleOutputCurrent102030mA

OutputComplianceRange1.0V

OutputResistanceTBD

kΩ

ANALOGOUTPUTS

OutputCapacitanceTBDpF

OfftTBD

ppm/°C

GainTBD

ppm/°C

TEMPERATUREDRIFT

ReferenceVoltageTBD

ppm/°C

InternalReferenceVoltage1.2V

REFERENCE

OutputCurrent100nA

VDDA333.133.33.47V

ANALOGSUPPLY

VOLTAGES

VDDA181.701.81.90V

VDDD333.133.33.47V

VDDD181.701.81.90V

DIGITALSUPPLY

VOLTAGES

VDDCLK1.701.81.90V

600MSPSTBDmWPOWERCONSUMPTION

StandbyPowerTBDmW

Table1:DCSpecifications

1Specificationssubjecttochangewithoutnotice

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AD9779PreliminaryTechnicalData

|Page4of34

DIGITALSPECIFICATIONS

(VDD33=3.3V,VDD18=1.8V,MAXIMUMSAMPLERATE,UNLESSOTHERWISENOTED)

ParameterTempTestLevelMinTypMaxUnit

Differentialpeak-to-peakVoltage800mV

CommonModeVoltage400mV

DACCLOCKINPUT

(CLK+,CLK-)

MaximumClockRate1GSPS

MaximumClockRate(SCLK)40MHz

MaximumPulwidthhighTBDns

SERIALPERIPHERAL

INTERFACE

MaximumpulwidthlowTBDns

Table2:DigitalSpecifications

ACSPECIFICATIONS

(VDD33=3.3V,VDD18=1.8V,MAXIMUMSAMPLERATE,UNLESSOTHERWISENOTED)

ParameterTempTestLevelMinTypMaxUnit

OutputSettlingTime(tst)(to0.025%)TBDns

OutputRiTime(10%to90%)TBDns

OutputFallTime(90%to10%)TBDns

DYNAMIC

PERFORMANCE

OutputNoi(IoutFS=20mA)TBDpA/rtHz

fDAC=100MSPS,fOUT=20MHz82dBc

fDAC=200MSPS,fOUT=50MHz82dBc

fDAC=400MSPS,fOUT=70MHz84dBc

SPURIOUSFREE

DYNAMICRANGE

(SFDR)

fDAC=800MSPS,fOUT=70MHz87dBc

fDAC=200MSPS,fOUT=50MHz91dBc

fDAC=400MSPS,fOUT=60MHz88dBc

fDAC=400MSPS,fOUT=80MHz81dBc

TWO-TONE

INTERMODULATION

DISTORTION(IMD)

fDAC=800MSPS,fOUT=100MHz88dBc

fDAC=156MSPS,fOUT=60MHz-158dBm/Hz

fDAC=200MSPS,fOUT=80MHz-157dBm/Hz

fDAC=312MSPS,fOUT=100MHz-159dBm/Hz

NOISESPECTRAL

DENSITY(NSD)

fDAC=400MSPS,fOUT=100MHz-159dBm/Hz

fDAC=245.76MSPS,fOUT=20MHz80dBc

fDAC=491.52MSPS,fOUT=100MHz79dBc

WCDMAADJACENT

CHANNELLEAKAGE

RATIO(ACLR),SINGLE

CARRIER

fDAC=491.52MSPS,fOUT=200MHz74dBc

fDAC=245.76MSPS,fOUT=60MHz78dBc

fDAC=491.52MSPS,fOUT=100MHz80dBc

WCDMASECOND

ADJACENTCHANNEL

LEAKAGERATIO

(ACLR),SINGLE

CARRIER

fDAC=491.52MSPS,fOUT=200MHz76dBc

Table3:ACSpecifications

元器件交易网

PreliminaryTechnicalDataAD9779

|Page5of34

PINFUNCTIONDESCRIPTIONS

Pin

No.

N

ameDescriptionPin

No.

N

ameDescription

1VDDC181.8VClockSupply51P2D<6>Port2DataInputD6

2VDDC181.8VClockSupply52P2D<5>Port2DataInputD5

3VSSCClockCommon53VDDD181.8VDigitalSupply

4VSSCClockCommon54VSSDDigitalCommon

5CLK+DifferentialClockInput55P1D<4>Port2DataInputD4

6CLK-DifferentialClockInput56P1D<3>Port2DataInputD3

7VSSCClockCommon57P1D<2>Port2DataInputD2

8VSSCClockCommon58P1D<1>Port2DataInputD1

9VDDC181.8VClockSupply59P1D<0>Port2DataInputD0(LSB)

10VDDC181.8VClockSupply60VDDD181.8VDigitalSupply

11VSSCClockCommon61VDDD333.3VDigitalSupply

12VSSCClockCommon62SYNC_O-DifferentialSynchronizationOutput

13SYNC_I+DifferentialSynchronizationInput63SYNC_O+DifferentialSynchronizationOutput

14SYNC_I-DifferentialSynchronizationInput64VSSDDigitalCommon

15VSSDDigitalCommon65PLL_LOCKPLLLockIndicator

16VDDD333.3VDigitalSupply66SPI_SDOSPIPortDataOutput

17P1D<15>Port1DataInputD15(MSB)67SPI_SDIOSPIPortDataInput/Output

18P1D<14>Port1DataInputD1468SPI_CLKSPIPortClock

19P1D<13>Port1DataInputD1369SPI_CSBSPIPortChipSelectBar

20P1D<12>Port1DataInputD1270RESETRet

21P1D<11>Port1DataInputD1171IRQInterruptRequest

22VSSDDigitalCommon72VSSAnalogCommon

23VDDD181.8VDigitalSupply73IPTATReferenceCurrent

24P1D<10>Port1DataInputD1074VREFVoltageReferenceOutput

25P1D<9>Port1DataInputD975I120

120µAReferenceCurrent

26P1D<8>Port1DataInputD876VDDA333.3VAnalogSupply

27P1D<7>Port1DataInputD777VSSAAnalogCommon

28P1D<6>Port1DataInputD678VDDA333.3VAnalogSupply

29P1D<5>Port1DataInputD579VSSAAnalogCommon

30P1D<4>Port1DataInputD480VDDA333.3VAnalogSupply

31P1D<3>Port1DataInputD381VSSAAnalogCommon

32VSSDDigitalCommon82VSSAAnalogCommon

33VDDD181.8VDigitalSupply83IOUT2_PDifferentialDACCurrentOutput,Channel2

34P1D<2>Port1DataInputD284IOUT2_NDifferentialDACCurrentOutput,Channel2

35P1D<1>Port1DataInputD185VSSAAnalogCommon

36P1D<0>Port1DataInputD0(LSB)86AUX2_PAuxiliaryDACVoltageOutput,Channel2

37DATACLK_OUTDataClockOutput87AUX2_NAuxiliaryDACVoltageOutput,Channel2

38VDDD333.3VDigitalSupply88VSSAAnalogCommon

39TXENABLETransmitEnable89AUX1_NAuxiliaryDACVoltageOutput,Channel1

40P2D<15>Port2DataInputD15(MSB)90AUX1_PAuxiliaryDACVoltageOutput,Channel1

41P2D<14>Port2DataInputD1491VSSAAnalogCommon

42P2D<13>Port2DataInputD1392IOUT1_NDifferentialDACCurrentOutput,Channel1

43VDDD181.8VDigitalSupply93IOUT1_PDifferentialDACCurrentOutput,Channel1

44VSSDDigitalCommon94VSSAAnalogCommon

45P2D<12>Port2DataInputD1295VSSAAnalogCommon

46P2D<11>Port2DataInputD1196VDDA333.3VAnalogSupply

47P2D<10>Port2DataInputD1097VSSAAnalogCommon

48P2D<9>Port2DataInputD998VDDA333.3VAnalogSupply

49P2D<8>Port2DataInputD899VSSAAnalogCommon

50P2D<7>Port2DataInputD7100VDDA333.3VAnalogSupply

Table4:PinFunctionDescriptions

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AD9779PreliminaryTechnicalData

|Page6of34

PINCONFIGURATION

VDDD18

VDDD18

VSSD

P2D<5>

P2D<4>

P2D<3>

P2D<2>

P2D<1>

P2D<0>

SYNC_O-

SPI_SDO

SPI_SDI

51

52

53

54

V

D

D

A

3

3

V

S

S

A

V

D

D

A

3

3

V

S

S

A

V

D

D

A

3

3

V

S

S

A

A

U

X

2

_

P

A

U

X

2

_

N

V

S

S

A

I

O

U

T

2

_

P

I

O

U

T

2

_

N

V

S

S

A

V

S

S

A

V

S

S

A

I

O

U

T

1

_

N

I

O

U

T

1

_

P

V

S

S

A

A

U

X

1

_

N

7

6

7

7

7

8

7

9

VSSD

VDDD33

VSSD

VDDD18

P1D<10>

P1D<11>

P1D<12>

P1D<13>

P1D<14>

P1D<15>

SYNC_I-

SYNC_I+

VSSC

VSSC

P

2

D

<

1

1

>

V

D

D

D

3

3

P

2

D

<

1

2

>

P

2

D

<

1

3

>

P

2

D

<

1

4

>

P

2

D

<

1

5

>

D

C

L

K

P

1

D

<

0

>

P

1

D

<

1

>

P

1

D

<

2

>

P

1

D

<

3

>

V

D

D

D

1

8

V

S

S

D

P

1

D

<

4

>

P

1

D

<

5

>

P

1

D

<

6

>

P

1

D

<

7

>

P

1

D

<

8

>

P1D<9>

2

7

2

6

P

2

D

<

7

>

P

2

D

<

8

>

P

2

D

<

9

>

P

2

D

<

1

0

>

5

0

4

9

A

U

X

1

_

P

V

S

S

A

V

D

D

A

3

3

V

S

S

A

V

D

D

A

3

3

CLK-

CLK+

VDDC18

VSSC

VSSC

3

2

VDDC18

VSSC

VSSC

VDDC18

1VDDC18

25

24

75

74

1

0

0

9

9

SPI_CLK

SPI_CSB

RESET

IPTAT

VREF

IRQ

AD9779

V

S

S

A

V

D

D

A

3

3

SYNC_O+

VSSD

VSS

T

X

E

n

a

bl

e

P2D<6>

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

6

5

4

9

8

7

12

11

10

15

14

13

18

17

16

21

20

19

23

22

3

4

3

3

3

0

2

9

2

8

3

2

3

1

3

6

3

5

4

3

4

2

3

9

3

8

3

7

4

1

4

0

4

8

4

7

4

4

4

6

4

5

8

0

8

1

8

4

8

2

8

3

8

5

8

6

8

9

8

7

8

8

9

0

9

1

9

4

9

2

9

3

9

5

9

8

9

6

9

7

I120

PLL_LOCK

AnalogDomain

DigitalDomain

V

D

D

D

1

8

V

S

S

D

VDDD33

figuration

元器件交易网

PreliminaryTechnicalDataAD9779

|Page7of34

INTERPOLATIONFILTERCOEFFICIENTS

Table5:HalfbandFilter1

Lower

Coefficient

Upper

Coefficient

Integer

Value

H(1)H(55)-4

H(2)H(54)0

H(3)H(53)13

H(4)H(52)0

H(5)H(51)-34

H(6)H(50)0

H(7)H(49)72

H(8)H(48)0

H(9)H(47)-138

H(10)H(46)0

H(11)H(45)245

H(12)H(44)0

H(13)H(43)-408

H(14)H(42)0

H(15)H(41)650

H(16)H(40)0

H(17)H(39)-1003

H(18)H(38)0

H(19)H(37)1521

H(20)H(36)0

H(21)H(35)-2315

H(22)H(34)0

H(23)H(33)3671

H(24)H(32)0

H(25)H(31)-6642

H(26)H(30)0

H(27)H(29)20755

H(28)32768

Table6:HalfbandFilter2

Lower

Coefficient

Upper

Coefficient

Integer

Value

H(1)H(23)-2

H(2)H(22)0

H(3)H(21)17

H(4)H(20)0

H(5)H(19)-75

H(6)H(18)0

H(7)H(17)238

H(8)H(16)0

H(9)H(15)-660

H(10)H(14)0

H(11)H(13)2530

H(12)4096

Table7:HalfbandFilter3

Lower

Coefficient

Upper

Coefficient

Integer

Value

H(1)H(15)-39

H(2)H(14)0

H(3)H(13)273

H(4)H(12)0

H(5)H(11)-1102

H(6)H(10)0

H(7)H(9)4964

H(8)8192

Table8:InverSincFilter

Lower

Coefficient

Upper

Coefficient

Integer

Value

H(1)H(9)2

H(2)H(8)-4

H(3)H(7)10

H(4)H(6)-35

H(5)401

元器件交易网

AD9779PreliminaryTechnicalData

|Page8of34

INTERPOLATIONFILTERRESPONSECURVES

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

97792xInterpolation,LowPassResponto

±4xInputDataRate(DottedLinesIndicate1dBRoll-Off)

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

97794xInterpolation,LowPassResponto

±4xInputDataRate(DottedLinesIndicate1dBRoll-Off)

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

97798xInterpolation,LowPassResponto

±4xInputDataRate(DottedLinesIndicate1dBRoll-Off)

元器件交易网

PreliminaryTechnicalDataAD9779

|Page9of34

CHARACTERIZATIONDATA

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

5763276844465536

Code

I

N

L

(

L

S

B

s

)

9779TypicalINL

-1

-0.5

0

0.5

1

1.5

2

5763276844465536

Code

D

N

L

(

L

S

B

s

)

9779TypicalDNL

50

60

70

80

90

100

Fout-MHz

S

F

D

R

-

d

B

m

F

DATA

=100MSPS

F

DATA

=160MSPS

F

DATA

=200MSPS

,1xInterpolation

50

55

60

65

70

75

80

85

90

95

100

Fout-MHz

S

F

D

R

-

d

B

m

F

DATA

=100MSPS

F

DATA

=160MSPS

F

DATA

=200MSPS

,2xInterpolation

50

55

60

65

70

75

80

85

90

95

100

020406080

Fout-MHz

S

F

D

R

-

d

B

m

F

DATA

=100MSPS

F

DATA

=125MSPS

F

DATA

=150MSPS

F

DATA

=200MSPS

,4xInterpolation

50

60

70

80

90

100

Fout-MHz

S

F

D

R

-

d

B

m

50MSPS

75MSPS

F

DATA

=62.5MSPS

100MSPS

,8xInterpolation

元器件交易网

AD9779PreliminaryTechnicalData

|Page10of34

50.0

60.0

70.0

80.0

90.0

100.0

020406080

Fout-MHz

I

M

D

-

d

B

c

F

DATA

=160MSPS

F

DATA

=200MSPS

,1xInterpolation

50.0

60.0

70.0

80.0

90.0

100.0

120

Fout-MHz

I

M

D

-

d

B

c

F

DATA

=160MSPS

F

DATA

=200MSPS

,2xInterpolation

50

60

70

80

90

100

60400

Fout-MHz

I

M

D

-

d

B

c

F

DATA

=100MSPS

F

DATA

=125MSPS

F

DATA

=150MSPS

F

DATA

=200MSPS

,4xInterpolation

50

60

70

80

90

100

250

Fout-MHz

I

M

D

-

d

B

c

50MSPS

100MSPS

F

DATA

=62.5MSPS

112.5MSPS

75MSPS

,8xInterpolation

-170

-168

-166

-164

-162

-160

-158

-156

-154

-152

-150

0708090

Fout-MHz

N

S

D

-

d

B

m/

H

z

F

DATA

=78MSPS

F

DATA

=156MSPS

F

DATA

=200MSPS

,1xInterpolation

-170

-168

-166

-164

-162

-160

-158

-156

-154

-152

-150

12

Fout-MHz

N

S

D

-

d

B

m/

H

z

F

DATA

=78MSPS

F

DATA

=156MSPS

F

DATA

=200MSPS

,2xInterpolation

元器件交易网

PreliminaryTechnicalDataAD9779

|Page11of34

-90

-85

-80

-75

-70

-65

-60

-55

-50

120300

Fout-MHz

A

C

L

R

-

d

B

c

F

DATA

=122.88MSPS

F

DATA

=61.44MSPS

r1stAdjacentBandWCDMA,-Chip

ModulationisudtotranslatebabandsignaltoIF.

-90

-85

-80

-75

-70

-65

-60

-55

-50

120300

Fout-MHz

A

C

L

R

-

d

B

c

F

DATA

=122.88MSPS

F

DATA

=61.44MSPS

r2ndAdjacentBandWCDMA,-Chip

ModulationisudtotranslatebabandsignaltoIF.

-90

-85

-80

-75

-70

-65

-60

-55

-50

120300

Fout-MHz

A

C

L

R

-

d

B

c

F

DATA

=122.88MSPS

F

DATA

=61.44MSPS

r3rdAdjacentBandWCDMA,-Chip

ModulationisudtotranslatebabandsignaltoIF.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

5150

F

DATA

(MSPS)

P

o

w

e

r

-

W

8xInterpolation,

ZeroStuffing

4xInterpolation,

ZeroStuffing

4xInterpolation

2xInterpolation,

ZeroStuffing

2xInterpolation

1xInterpolation,

ZeroStuffing

1xInterpolation

8xInterpolation

issipation,SingleDACMode

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

5150

F

DATA

(MSPS)

P

o

w

e

r

-

W

8xInterpolation,

ZeroStuffing

8xInterpolation,F

DAC

/4Modulation

4xInterpolation,

ZeroStuffing

8xInterpolation,F

DAC

/2Modulation

8xInterpolation,F

DAC

/8Modulation

8xInterpolation,Modulationoff

4xInterpolation,F

DAC

/4Modulation

4xInterpolation,F

DAC

/2Modulation

4xInterpolation,Modulationoff

2xInterpolation,

ZeroStuffing

2xInterpolation,F

DAC

/2Modulation

2xInterpolation,Modulationoff

1xInterpolation,

ZeroStuffing

1xInterpolation

issipation,DualDACMode

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

010001200

F

DAC

-MSPS

P

o

w

e

r

-

W

issipationofInverSincFilter

元器件交易网

AD9779PreliminaryTechnicalData

|Page12of34

GENERALDESCRIPTION

TheAD9779combinesmanyfeatureswhichmakeitmakeitavery

attractiveDACforwiredandwirelesscommunicationssystems.

ThedualdigitalsignalpathanddualDACstructureallowaneasy

interfacewithcommonquadraturemodulatorswhendesigning

edandperformanceofthe

AD9779allowwiderbandwidths/morecarrierstobesynthesized

italengineinthe

AD9779usabreakthroughfilterarchitecturethatcombinesthe

lowsthe

AD9779alsohasfeatureswhichallowsimplifiedsynchronization

withincomingdata,andalsoallowsmultipleAD9779stobe

synchronized.

SerialPeripheralInterface

AD9779

SPI

PORT

SPI_CSB(pin69)

SPI_SCLK(pin68)

SPI_SDI(pin67)

SPI_SDO(pin66)

9779SPIPort

TheAD9779rialportisaflexible,synchronousrial

communicationsportallowingeasyinterfacetomanyindustry-

ialI/Ois

compatiblewithmostsynchronoustransferformats,includingboth

theMotorolaSPI®andIntel®erfaceallows

read/

ormultiplebytetransfersaresupported,aswellasMSBfirstorLSB

9779’srialinterfaceportcanbe

configuredasasinglepinI/O(SDIO)ortwounidirectionalpinsfor

in/out(SDIO/SDO).

GeneralOperationoftheSerialInterface

TherearetwophastoacommunicationcyclewiththeAD9779.

Pha1istheinstructioncycle,whichisthewritingofan

instructionbyteintotheAD9779,coincidentwiththefirsteight

tructionbyteprovidestheAD9779rial

portcontrollerwithinformationregardingthedatatransfercycle,

1

instructionbytedefineswhethertheupcomingdatatransferisread

orwrite,thenumberofbytesinthedatatransfer,andthestarting

steight

SCLKrisingedgesofeachcommunicationcycleareudtowrite

theinstructionbyteintotheAD9779.

AlogichighontheCSpin,followedbyalogiclow,willretthe

trueregardlessoftheprentstateoftheinternalregistersorthe

PI

portisinthemidstofaninstructioncycleoradatatransfer

cycle,noneoftheprentdatawillbewritten.

TheremainingSCLKedgesareforPha2ofthecommunication

2istheactualdatatransferbetweentheAD9779and

2ofthecommunicationcycleisa

transferof1,2,3,or4databytesasdeterminedbytheinstruction

bytedatatransfersareufultoreduceCPUoverheadwhen

erschangeimmediately

uponwritingtothelastbitofeachtransferbyte.

InstructionByte

TheinstructionbytecontainstheinformationshowninError!

Referencesourcenotfound..

MSBLSB

I7I6I5I4I3I2I1I0

R/WN1N0A4A3A2A1A0

tructionByte

R/W,Bit7oftheinstructionbyte,determineswhetherareadora

0indicatesawriteoperation.

N1,N0,Bits6and5oftheinstructionbyte,determinethenumber

decodesareshowninTable10.

A4,A3,A2,A1,A0,Bits4,3,2,1,0oftheinstructionbyte,

determinewhichregisterisaccesdduringthedatatransfer

tibytetransfers,this

ainingregister

addressaregeneratedbytheAD9779badontheLSBFIRSTbit

(REG00,bit6).

N1N2Description

00Transfer1Byte

01Transfer2Bytes

10Transfer3Bytes

11Transfer4Bytes

ansferCount

SerialInterfacePortPinDescriptions

SCLK—ialclockpinisudtosynchronize

datatoandfromtheAD9779andtoruntheinternalstate

’ainput

ais

drivenoutoftheAD9779onthefallingedgeofSCLK.

CSB—lowinputstartsandgatesa

wsmorethanonedevicetobeudon

andSDIOpinswill

lect

shouldstaylowduringtheentirecommunicationcycle.

SDIO—SerialDataI/alwayswrittenintotheAD9779on

元器件交易网

PreliminaryTechnicalDataAD9779

|Page13of34

r,thispincanbeudasabidirectionaldataline.

TheconfigurationofthispiniscontrolledbyBit7ofregister

aultisLogic0,whichconfigurestheSDIOpin

asunidirectional.

SDO—readfromthispinforprotocols

cawheretheAD9779operatesinasinglebidirectionalI/Omode,

thispindoesnotoutputdataandisttoahighimpedancestate.

MSB/LSBTransfers

TheAD9779rialportcansupportbothmostsignificantbit

(MSB)firstorleastsignificantbit(LSB)

functionalityiscontrolledbyregisterbitLSBFIRST(REG00,bit6).

ThedefaultisMSBfirst(LSBFIRST=0).

WhenLSBFIRST=0(MSBfirst)theinstructionanddatabytes

mustbewrittenfrommostsignificantbittoleastsignificantbit.

MultibytedatatransfersinMSBfirstformatstartwithan

instructionbytethatincludestheregisteraddressofthemost

uentdatabytesshouldfollowinorder

irstmode,therial

portinternalbyteaddressgeneratordecrementsforeachdatabyte

ofthemultibytecommunicationcycle.

WhenLSBFIRST=1(LSBfirst)theinstructionanddatabytes

mustbewrittenfromleastsignificantbittomostsignificantbit.

MultibytedatatransfersinLSBfirstformatstartwithan

instructionbytethatincludestheregisteraddressoftheleast

ialport

internalbyteaddressgeneratorincrementsforeachbyteofthe

multibytecommunicationcycle.

TheAD9779rialportcontrollerdataaddresswilldecrement

fromthedataaddresswrittentoward0x00formultibyteI/O

ialportcontroller

addresswillincrementfromthedataaddresswrittentoward0x1F

formultibyteI/OoperationsiftheLSBfirstmodeisactive.

NotesonSerialPortOperation

TheAD9779rialportconfigurationiscontrolledbyREG00,bits

portanttonotethattheconfigurationchanges

multibytetransfers,writingtothisregistermayoccurduringthe

stbetakentocompensate

forthisnewconfigurationfortheremainingbytesofthecurrent

communicationcycle.

Thesameconsiderationsapplytottingthesoftwareret,RESET

(REG00,bit5).AllregistersarettotheirdefaultvaluesEXCEPT

REG00andREG04whichremainunchanged.

Uofonlysinglebytetransferswhenchangingrialport

configurationsorinitiatingasoftwareretisrecommendedto

preventunexpecteddevicebehavior.

R/WN0N1A0A1A2A3A4D7D6

N

D5

N

D0

0

D1

0

D2

0

D3

0

D7D6

N

D5

N

D0

0

D1

0

D2

0

D3

0

INSTRUCTIONCYCLEDATATRANSFERCYCLE

CSB

SCLK

SDIO

SDO

0

3

1

5

2

-

0

-

0

0

4

RegisterInterfaceTimingMSBFirst

A0A1A2A3A4N1N0R/WD0

0

D1

0

D2

0

D7

N

D6

N

D5

N

D4

N

D0

0

D1

0

D2

0

D7

N

D6

N

D5

N

D4

N

INSTRUCTIONCYCLEDATATRANSFERCYCLE

CSB

SCLK

SDIO

SDO

0

3

1

5

2

-

0

-

0

0

5

RegisterInterfaceTimingLSBFirst

INSTRUCTIONBIT6INSTRUCTIONBIT7

CSB

SCLK

SDIO

t

DS

t

DSt

DH

t

PWH

t

PWL

t

SCLK

0

3

1

5

2

-

Pr

D-

0

0

6

DiagramforSPIRegisterWrite

DATABITn–1DATABITn

CSB

SCLK

SDIO

SDO

0

3

1

5

2

-

Pr

D-

0

0

7t

DV

DiagramforSPIRegisterRead

元器件交易网

AD9779PreliminaryTechnicalData

|Page14of34

SPIRegisterMap

Register

Name

AddressBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Default

Comm

Register

00h00SDIO

Bidirectional

LSB,MSBFirstSoftware

Ret

Power

Down

Mode

Auto

Power

Down

Enable

PLLLock

Indicator

00h

01h01FilterInterpolationFactor

<1:0>

FilterInterpolationMode<4:0>Zero

Stuffing

Enable

00h

Digital

Control

Register

02h02DataFormatOnePort

Mode

RealModeInver

Sinc

Enable

DATACLK

Invert

IQSelect

Invert

QFirst00h

03h03DataDelayMode<1:0>DataClockDelay<2:0>DataWindowDelay<2:0>00h

04h04SyncOutDelay<3:0>SyncWindowDelay<3:0>00h

Sync

Control

05h05SyncEnableSyncDriver

Enable

DacClockOfft<2:0>00h

Interrupt

Register

06h06DataDelay

IRQ

SyncDelay

IRQ

Cross

ControlIRQ

DataDelay

IRQEnable

SyncDelay

IRQEnable

Cross

ControlIRQ

Enable

00h

07h07PLLBandSelect<4:0>PLLLoopCapSelect<2:0>CFh

PLLControl

08h08PLLEnablePLLOutputFreqDivide

<1:0>

PLLLoopFreqDivide

<1:0>

PLLLoopFilterPole/Zero<2:0>37h

Misc.

Control

Register

09h24PLLError

Source

PLLRef

Bypass

PLLGain<2:0>PLLBias<2:0>38h

0Ah09IDACGainAdjustment<7:0>F9h

IDAC

Control

Register

0Bh10IDACSLEEPIDACPower

Down

IDACGainAdjustment

<9:8>

01h

0Ch11AuxiliaryDAC1Data<7:0>00h

Aux1DAC

Control

Register

0Dh12Auxiliary

DAC1Sign

Auxiliary

DAC1

Current

Direction

Auxiliary

DAC1Sleep

AuxiliaryDAC1Data

<9:8>

00h

0Eh13QDACGainAdjustment<7;0>F9h

QDAC

Control

Register

0Fh14QDACSLEEPQDACSleepQDACGainAdjustment

<9:8>

01h

元器件交易网

PreliminaryTechnicalDataAD9779

|Page15of34

10h15AuxiliaryDAC2Data<7:0>00h

Aux2DAC

Control

Register

11h16Auxiliary

DAC2Sign

Auxiliary

DAC2

Current

Direction

Auxiliary

DAC2Power

Down

AuxiliaryDAC2Data

<9:8>

00h

12h17CrossUpdel<7:0>00h

13h18CrossDndel<7:0>00h

14h19CrossClockDivide<3:0>CrossWiggleDelay<3:0>00h

Cross

Register

15h20CrossRun

CrossStatusCrossDone

CrossWiggle<2:0>CrossStep<1:0>00h

Analog

Write

16h23AnalogWrite<7:0>00h

17h21MirrorRollOff<1:0>BandGapTrim<2:0>00h

Analog

Control

Register

18h22StackHeadroomControl<7:0>CAh

Analog

Status

Register

19h25

AnalogStatus<7:0>

--h

Test1

Register

1Ah26MISREnableMISRIQ

Select

MISR

Samples

Internal

Data

Enable

TestMode<2:0>00h

1Bh27

BIST<31:24>

--h

1Ch28

BIST<23:16>

--h

1Dh29

BIST<15:8>

--h

Test2

Register

1Eh30

BIST<7:0>

--h

Table11:SPIRegisterMap

元器件交易网

AD9779PreliminaryTechnicalData

|Page16of34

Register(hex)BitsNameFunctionDefault

7SDIOBidirectional0:USDIOpinasinputdataonly

1:USDIOasbothinputandoutputdata

0

6LSB/MSBFirst0:FirstbitofrialdataisMSBofdatabyte

1:FirstbitofrialdataisLSBofdatabyte

0

5SoftwareRESETBitmustbewrittenwitha1,then0tosoftretSPIregistermap0

4PowerDown

Mode

0:Allcircuitryisactive

1:Disablealldigitalandanalogcircuitry,onlySPIportisactive

0

3AutoPowerDown

Enable

0

00

CommRegister

1PLLLOCK(read

only)

0:PLLisnotlocked

1:PLLislocked

0

7:6

F

ilterInterpolation

Rate

00:1xinterpolation

01:2xinterpolation

10:4xinterpolation

11:8xinterpolation

00

5:2ControlHalfband

Filters1,2,3

SeeTable13forfiltermodes

0000

01

DigitalPathFilter

Control

0ZeroStuffing0:Zerostuffingoff

1:Zerostuffingon

0

7DataFormat0:Signedbinary

1:Unsignedbinary

0

6OnePortMode0:Bothinputdataportsreceivedata

1:Dataport1onlyreceivesdata

0

5RealMode0:EnableQpathforsignalprocessing

1:DisableQpathdata(clocksdisabled)

0

3InverSinc

Enable

0:Inversincdisabled

1:Inversincdisabled

0

2DATACLKInvert0:OutputDATACLKsamephaasinternalcaptureclock

1:OutputDATACLKoppositephaasinternalcaptureclock

0

1IQSelectInvert0:TxEnable(pin39)=1,routesinputdatatoIchannel

TxEnable(pin39)=0,routesinputdatatoQchannel

1:TxEnable(pin39)=1,routesinputdatatoQchannel

TxEnable(pin39)=0,routesinputdatatoIchannel

0

02

GeneralMode

Control

0QFirst0:FirstbyteofdataisalwaysIdataatbeginningoftransmit

1:FirstbyteofdataisalwaysQdataatbeginningoftransmit

7:6DataDelayMode00:Manual,noerrorcorrection

01:Manual,continuourrorcorrection

10:automatic,onepasscheck

11:automatic,continuouspasscheck

00

5:3DataClockDelayDataClockdelaycontrol000

03

DataClockDelay

2:0DataWindow

Delay

Windowdelaycontrol000

7:4SyncOutputDelay0000

04

Synchronization

Delay

3:0SyncWindow

Delay

0000

7SyncEnable0:LVDSandsynchronizationrceiverlogicoff

1:LVDSandsynchronizationrceiverlogicon

0

6SyncDriverEnable0:LVDSdriveroff

1:LVDSdriveron

0

05

ChipSyncandData

DelayControl

5:3DACClockOfft0

元器件交易网

PreliminaryTechnicalDataAD9779

|Page17of34

7DataDelayError

(readonly)

0

6Chip

Synchronization

DelayError(read

only)

0

5CrossControl

Error(readonly)

0

3DataDelayError

Enable

0

2Chip

Synchronization

ErrorEnable

0

06

IRQStatus

1CrossControl

ErrorEnable

0

7:3PLLBandSelect

SeeTable14for

values.

11001

07

PLLBandandDivide

2:0PLLRippleCap

Adjust

111

7PLLEnable0:PLLoff,DACrateclocksuppliedbyoutsidesource

1:PLLon,DACrateclocksynthesizedinternallyfromdatarateclockviaPLL

clockmultiplier

0

6:5PLLOutputDivide

Ratio

00:Divideby1

01:Divideby2

10:Divideby4

11:Divideby8

01

4:3PLLLoop

FeedbackDivide

Ratio

00:Divideby1

01:Divideby2

10:Divideby4

11:Divideby8

10

08

PLLEnableand

ChargePump

Control

2:0PLLLoopFilter

BandwidthTuning

Recommended

Table14forPLL

BandSelect

values.

000:PLLbandlect00000-00111

100:PLLbandlect01000-01111

110:PLLbandlect10000-10111

111:PLLbandlect11000-11111

111

7PLLErrorBit

Source

0:Phaerrordetect

1:Rangelimit

0

6PLLReference

Bypass

0:UPLLreference

1:UDACreference

0

5:3VCOAGCGain

le

14forPLLBand

Selectvalues.

000:PLLbandlect00000-00111

100:PLLbandlect01000-01111

110:PLLbandlect10000-10111

111:PLLbandlect11000-11111

111

09

l

2:0PLLBiasCurrent

Level/Trim

000

0A

IDACGain

7:0IDACGain

Adjustment

(7:0)LSBsliceof10bitgainttingwordforIDAC11111001

7IDACSleep0:IDACon

1:IDACoff

0

6IDACPowerDown0:IDACon

1:IDACoff

0

0B

IDACGainand

Control

1:0IDACGain

Adjustment

(9:8)MSBsliceof10bitgainttingwordforIDAC01

0C

AuxiliaryDAC1Gain

7:0AuxDAC1Gain

Adjustment

(7:0)LSBsliceof10bitgainttingwordforAuxDAC100000000

元器件交易网

AD9779PreliminaryTechnicalData

|Page18of34

7AuxDAC1Sign0:Positive

1:Negative

0

6AuxDAC1

Direction

0:Source

1:Sink

0

5AuxDAC1Sleep0:AuxDAC1on

1:AuxDAC1off

0

0D

AuxiliaryDAC1

ControlandData

1:0AuxDAC1Gain

Adjustment

(9:8)MSBsliceof10bitgainttingwordforAuxDAC100

0E

QDACGain

7:0QDACGain

Adjustment

(7:0)LSBsliceof10bitgainttingwordforQDAC11111001

7QDACSleep0:QDACon

1:QDACoff

0

6QDACPower

Down

0:QDACon

1:QDACoff

0

0F

QDACGainand

Control

1:0QDACGain

Adjustment

(9:8)MSBsliceof10bitgainttingwordforQDAC01

10

AuxiliaryDAC2Gain

7:0AuxDAC2Gain

Adjustment

(7:0)LSBsliceof10bitgainttingwordforAuxDAC200000000

7AuxDAC2Sign0:Positive

1:Negative

0

6AuxDAC2

Direction

0:Source

1:Sink

0

5AuxDAC2Sleep0:AuxDAC1on

1:AuxDAC1off

0

11

AuxiliaryDAC2

ControlandData

1:0AuxDAC2Gain

Adjustment

(9:8)MSBsliceof10bitgainttingwordforAuxDAC200

12

CrossPointUpper

Delay

7:0UpdelayValueabovezeroforuppercrossdelay(bits7,6,unud)00000000

13

CrossPointUpper

Delay

7:0DndelayValuebelowzeroforlowercrossdelay(bits7,6,unud)00000000

7:3CrossControl

ClockDelay

DividerateofCNTCLKby2^(3:0),CNTCLK=1/16DACclockrate00000

14

WiggleDelayfor

CrossPointControl

2:0WiggleDelayTimestepin2^(WiggleDelay)CNTCLKcycles000

7CrossRun0:DisablesCrossControlloop

1:EnablesCrossControlloop

0

6CrossStatus(read

only)

0:Controlloopisloweringcrosspoint

1:Controlloopisraisingcrosspoint

0

5CrossDone(read

only)

0:Controlloopischnagingcrosspointvalue

1:Controlloopisholdingcrosspointvalue

0

4:2CrossWiggle(2:0)Numberofiterationsallowedincontrolloop000

15

CrossPointControl

1:0CrossStep(1:0)Valuetochangecrosspointvalueperiteration(wiggle)00

16

AnalogWrite

7:0AnalogWriteProvidextrawriteablecontrolregistersforanalogcircuit00000000

7:6MirrorRolloff

Frequency

00

17

MirrorRolloffand

bandgapTrim

2:0BandGapTrim

Temperature

Characteristic

000

Outputstackheadroomcontrol

Overdrive(currentdensity)trim(temperaturepacking)

18

OutputStack

headroomControl

ReferenceofftfromVDD3V(vcascentering)

19

AnalogStatus

7:0AnalogStatusProvidextrastatusregisterforanalogcircuitry(unud,readonly)

元器件交易网

PreliminaryTechnicalDataAD9779

|Page19of34

7MISREnable0:MISRdisabled

1:MISREnabled

0

6MISRIQSelect0:ReadbackIpathsignature

1:ReadbackQpathsignature

0

5MISRSamples0:MISRusshortsampleperiod

1:MISRuslongsampleperiod

0

3InternalData

Enable

0:Internaldatageneratoroff

1:Internaldatageneratoron

0

1A

MISRControl

2:0TestMode000:Normaldataportoperation

001-111:Tobedefinedtestmodes

000

1B

MISRSignature

Register1

7:0MISRSignature(31:24)Sliceof32bitMISRsignature

1C

MISRSignature

Register2

7:0MISRSignature(23:16)Sliceof32bitMISRsignature

1D

MISRSignature

Register3

7:0MISRSignature(15:8)Sliceof32bitMISRsignature

1E

MISRSignature

Register4

7:0MISRSignature(7:0)Sliceof32bitMISRsignature

Table12:SPIRegisterDescription

元器件交易网

AD9779PreliminaryTechnicalData

|Page20of34

F_lowCenterF_HighInterp.

Factor

<7:6>

Filter

Mode

<5:2>

Filter1mode

(Mode_F1)

Filter2mode

(Mode_F2)

Filter3mode

(Mode_F3)

ModulationNyquist

Zone

Passband

(izedtoFDAC)

800h000DC_odd1-0.0500.05

801h110DC_even20.01250.06250.1125

802h221

F

/8_odd30.0750.1250.175

803h332

F

/8_even40.13750.18750.2375

In8x

interpolation,

BW=0.0375-

(0.1*FDAC)

Worstca:

F/32

804h0422

F

/8_odd50.20.250.3

805h1522

F

/8_even60.26250.31250.3625

806h2633

F

/8_odd70.3250.3750.425

807h3743

F

/8_even80.38750.43750.4875

808h004-4

F

/8_even-80.450.50.55

809h114-4

F

/8_odd-70.51250.56250.6125

80Ah225-3

F

/8_even-60.5750.6250.675

80Bh336-3

F

/8_odd-50.63750.68750.7375

80Ch046-2

F

/8_even-40.70.750.8

80Dh156-2

F

/8_odd-30.76250.81250.8625

80Eh267-

F

/8_even-20.8250.8750.925

80

F

h370-

F

/8_odd-10.88750.93750.9875

400h00O

FF

DC_odd1-0.100.1

401h11O

FF

DC_even20.0250.1250.225

402h22O

FFF

/4_odd30.150.250.35

403h33O

FFF

/4_even40.2750.3750.475

In8x

interpolation,

BW=0.075-(0.2*

FDAC)

Worstca:

F/16

404h04O

FF

-

F

/2_even-40.40.50.6

405h15O

FF

-

F

/2_odd-30.5250.6250.725

406h26O

FF

-

F

/4_even-20.650.750.85

407h37O

FF

-

F

/4_odd-10.7750.8750.975

200h0O

FF

O

FF

DC_odd1-0.200.2

201h1O

FF

O

FF

DC_even20.050.250.45

202h2O

FF

O

FF

-

F

/2_even-10.30.50.7

203h3O

FF

O

FF

-

F

/2_odd-20.550.750.95

In2x

Interpolation

BW=0.15-0.4

FDAC

Worstca:F/8

Table13:InterpolationFilterModes,eReg01,bits5:2

元器件交易网

PreliminaryTechnicalDataAD9779

|Page21of34

PLLFrequencyBandSelect

PLLBandSelectValueFrequencyinMHz

11111(31)804–850

11110(30)827–875

11101(29)850–899

11100(28)875–925

11011(27)899–951

11010(26)925–977

11001(25)951–1005

11000(24)977–1032

10111(23)1004–1061

10110(22)1032–1089

10101(21)1060–1119

10100(20)1089–1149

10011(19)1118–1179

10010(18)1148–1210

10001(17)1176–1239

10000(16)1206–1270

01111(15)1237–1302

01110(14)1268–1334

01101(13)1299–1366

01100(12)1331–1399

01011(11)1363–1432

01010(10)1396–1466

01001(9)1425–1495

01000(8)1458–1529

00111(7)1492–1563

00110(6)1525–1597

00101(5)1560–1632

00100(4)1594–1667

00011(3)1629–1702

00010(2)1665–1737

00001(1)1700–1773

00000(0)1735–1810

dSelectValue

元器件交易网

AD9779PreliminaryTechnicalData

|Page22of34

InternalReference/FullScaleCurrentGeneration

FullscalecurrentontheAD9779IDACandQDACcanbetfrom

lly,the1.2Vbandgapreferenceisudtotupa

currentinanexternalresistorconnectedtoI120(pin75).A

simplifiedblockdiagramoftheAD9779referencecircuitryisgiven

ommendedvaluefortheexternalresistor

is10KΩ,whichtsupanIREFERENCEintheresistorof120µa.

Internalcurrentmirrorsprovideacurrentgainscaling,where

IDACorQDACgainisa10bitwordintheSPIportregister

(registers0A,0B,0E,and0F).ThedefaultvaluefortheDACgain

registersgivesanIFSof20ma.

1.2Vbandgap

10KΩ

0.1µF

currentscaling

DACfullscale

referencecurrent

IDAC

QDAC

AD9779

IDACgain

QDACgain

I120

VREF

nceCircuitry

whereIFSiqualto;

32gainDAC

1024

6

12

27

R

1.2V

×

⎟

⎟

⎠

⎞

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

×+×

0

5

10

15

20

25

30

35

01000

DACgaincode

I

F

S

(

m

a

)

nCode

AuxiliaryDACs

lscale

outputcurrentontheDACsisderivedfromthe1.2Vbandgap

nscalefromthereference

amplifiertotheDACreferencecurrentforeachauxDACis16.67.

withtheAuxDACgainttofullscale(10bitvalues,SPIreg0C,

0D,10,11),thisgivesafullscalecurrentof2maforAuxDAC1and

hthesameSPIportregisters,theAux

DACscanbeturnedoff,theirsignscanbeinverted(scaleis

reverd,0-1024givesIFSto0),andtheycanbeprogrammedfor

urcingcurrent,theoutput

compliancevoltageis0-1.5V,andwhensinkingcurrenttheoutput

compliancevoltageis0.8-1.5V.

TheAuxDACscanbeudforLOcancellationwhentheDAC

alDACtoQuadrature

,theinputcommon

modevoltageforthemodulatorismuchhigherthantheoutput

compliancerangeoftheDAC,

inputreferredofftvoltageoftheequadraturemodulatorcan

resultinLOfeedthroughonthemodulatoroutput,degrading

system,onfigurationofFigure29isud,the

AuxDACscanbeudtocompensatefortheinputDCofftofthe

quadmod,thusreducingLOfeedthrough.

IOUT1_P

IDAC

QDAC

IOUT2_N

IOUT2_P

IOUT1_N

AUX1_P

AUX

DAC1

AUX2_N

AUX2_P

AUX1_N

AUX

DAC2

QuadMod

IInputs

QuadMod

QInputs

lUofAuxiliaryDACs

PowerDownandSleepModes

TheAD9779hasavarietyofpowerdownmodes,sothatthedigital

engine,mainTxDACs,orauxiliaryDACscanbepowereddown

individually,SPIport,themainTxDACscan

pmode,the

TxDACoutputisturnedoff,

referenceremainspoweredonthough,sothatrecoveryfromsleep

eTxDACisplacedinPowerDown

mode,

modeoffersmoresubstantialpowersavingsthaninsleepmode,

iliaryDACsalso

havethecapabilitytobeprogrammedviatheSPIportintosleep

mode.

元器件交易网

PreliminaryTechnicalDataAD9779

|Page23of34

Thepowerdownbit(register00h,bit4)controlsthepowerdown

erdown

functioninbit4worksinconjunctionwithTxEnable(pin39)

accordingtothefollowing;

TxEnable=

0:PWDWN=

0:Flushdatapathwithzeroes

1:Digitalengineinpowerdownstate,DACsand

referencearenotaffected.

1:Normaloperation

InternalPLLClockMultiplier/ClockDistribution

TheinternalclockstructureontheAD9779allowstheurtodrive

thedifferentialclockinputswithaclockat1xoranintegermultiple

oftheinputdatarate,

internaltotheAD9779providesinputclockmultiplicationand

providesalloftheinternalclocksrequiredfortheinterpolation

filtersanddatasynchronization.

ock

inputcanberundifferentially,orsingledendedbydrivingpin5

withaclocksignal,andbiasingpin6tothemidswingpointofthe

revariousconfigurationsinwhichthisclock

architecturecanberun;

bled(reg08h,bit7=1)–ThePLLenableswitch

inFigure32isconnectedtothejunctionofthedividers

rN3determinestheinterpolationrate

oftheDAC,andtheratioN2/N3determinestheratioof

ReferenceClock/runs

optimallyovertherange804MHzto1800MHz,sothat

N1isudtokeepthespeedoftheVCOinthisrange,

p

filtercomponentsareentirelyinternalandnoexternal

compensationisnecessary.

abled(reg08h,bit7=0)–ThePLLenableswitch

inFigure32isconnectedtotheReferenceClockInput.

ThedifferentialreferenceclockinputwillbetheDAC

outputsamplerateandN3willdeterminethe

interpolationrate.

alClockArchitectureofAD9779

TimingInformation

Figure33throughFigure35showsomeofthevarioustiming

binationofthe

ttingsofN2andN3meansthatthereferenceclockfrequency

33through

Figure35show,respectively,whatthetiminglookslikewhen

N2/N3=1,2,and4.

Figure36showsthetimingspecificationsfortheAD9779whenthe

erenceclockisattheDACoutputsample

xampleshowninFigure36,ifthePLLisdisabled,the

interpolationis4x..Thetupandholdtimefortheinputdataare

withrespecttotherisingedgeofthereferenceclockwhichoccurs

atifreg

02h,bit2ist,DATACLKoutisinvertedsothelatchingreference

clockedgewilloccurjustbeforetheDATACLKoutfallingedge.

tHtS

tD

ReferenceClock

DATACLKout

InputData

SpecificationsforAD9779,PLLEnabled,ReferenceClock=1xInputSampleRate

元器件交易网

AD9779PreliminaryTechnicalData

|Page24of34

tHtS

tD

ReferenceClock

DATACLKout

InputData

SpecificationsforAD9779,PLLEnabled,ReferenceClock=2xInputSampleRate

tHtS

tD

ReferenceClock

DATACLKout

InputData

SpecificationsforAD9779,PLLEnabled,ReferenceClock=4xInputSampleRate

tHtS

tD

tS=-2.3nstyp

tH=3.7nstyp

tD=5.5nstyp

ReferenceClock

DATACLKout

InputData

SpecificationsforAD9779,PLLDisabled,4xInterpolation

UsingDataDelaytoMeetTimingRequirements

Inordertomeetstricttimingrequirementsatinputdataratesofup

to250MSPS,ming

adjustmentscanbemadebyprogrammingvaluesintotheDATA

CLOCKDELAYregister(reg03h,5:3).Bychangingthevaluesin

thisregister,delaycanbeaddedtothedefaultdelaybetweenthe

ectofthisisshownin

Figure37andFigure38.

romDACCLKtoDATACLKoutwithCLKDATADELAY=000

Figure38..DelayfromDACCLKtoDATACLKoutwithCLKDATADELAY=111

ThedifferencebetweenthedefaultdelayofFigure37andthe

maximumdelayshowninFigure38istherangeprogrammablevia

ultingdelayswhen

programmingDATACLKDELAYbetween000and111area

linearextrapolationbetweenthetwofigures.(typically300ps-

400psperincrementtoDATACLKDELAY).

元器件交易网

PreliminaryTechnicalDataAD9779

|Page25of34

InterpolationFilterArchitecture

TheAD9779canprovideupto8×interpolationordisablethe

fficientsofthelowpassfilters

andtheinversincfilteraregiveninTable5,Table6,Table7,and

alplotsforthefilterresponsaregiveninFigure3,

Figure4,andFigure5.

Withtheinterpolationfilterandmodulatorcombined,the

incomingsignalcanbeplacedanywherewithintheNyquistregion

heinputsignaliscomplex,

thisarchitectureallowsmodulationoftheinputsignaltopositive

ornegativeNyquistregions(refertoTable13).

TheNyquistregionsupto4×theinputdataratecanbeenin

Figure39.

DC1×4×

3×2×

-2×-3×-4×-1×

1234-1-25786-3-4-5-6-7-8

tZones

Figure3,Figure4andFigure5showthelowpassresponofthe

ingonthe

modulationfeature,theresponofthedigitalfilterscanbetuned

ample,

Figure40toFigure46showtheoddmodefilterrespons(referto

Table13forodd/evenmodefilterrespons).

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof-4fDAC/8

FilterinOddMode

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof-3fDAC/8

FilterinOddMode

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof-2fDAC/8

FilterinOddMode

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof-1fDAC/8

FilterinOddMode

元器件交易网

AD9779PreliminaryTechnicalData

|Page26of34

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationoffDAC/8

FilterinOddMode

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof2fDAC/8

FilterinOddMode

-4-3-2-101234

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

olation/ModulationCombinationof3fDAC/8

FilterinOddMode

Evenmodefilterresponsallowthepassbandtobecentered

around±0.5,±1.5,±2.5and±ingfromandodd

moderespontoanevenmodefilterrespondoesnotmodulate

d,ample,

picturetheresponofFigure46,andassumethesignalinbandis

acomplexsignaloverthebandwidth3.2to3.3×ven

modefilterresponisthenlected,thepassbandwillnowbe

centeredat3.5×r,thesignalwillstillremainatthe

n/oddmodecapabilityallows

thepassbandtobeplacedanywhereintheDACNyquist

bandwidth.

TheAD9779isadualDACwithaninternalcomplexmodulator

ulatorcanbe

ttoarealoracomplexmodebyprogrammingregister02h,bit5.

Inthedefaultmode,bit5isttozeroandthemodulationis

9779thenexpectstherealandtheimaginary

componentsofacomplexsignalatdigitalinputportsoneandtwo

(IandQrespectively).TheDACoutputswillthenreprentthe

realandimaginarycomponentsoftheinputsignal,modulatedby

thecomplexcarrierFDAC/2,FDAC/4orFDAC/8.

WithBit5ttoone,annelisshut

offandit’

outputspectrumateithertheIDACortheQDACwillthen

reprentthesignalatdigitalinputportone,realmodulatedbythe

internaldigitalcarrier(FDAC/2,FDAC/4orFDAC/8).

元器件交易网

PreliminaryTechnicalDataAD9779

|Page27of34

EVALUATIONBOARDSCHEMATICS

9779EvalBoard,RevB,PowerSupplyDecouplingandSPIInterface

元器件交易网

AD9779PreliminaryTechnicalData

|Page28of34

9779EvalBoard,RevB,CircuitryLocaltoAD9779

元器件交易网

PreliminaryTechnicalDataAD9779

|Page29of34

9779EvalBoard,RevB,AD8349QuadratureModulator

元器件交易网

AD9779PreliminaryTechnicalData

|Page30of34

9779EvalBoard,RevB,DACClockInterface

元器件交易网

PreliminaryTechnicalDataAD9779

|Page31of34

9779EvalBoard,RevB,InputPort1,DigitalInputBuffers

元器件交易网

AD9779PreliminaryTechnicalData

|Page32of34

9779EvalBoard,RevB,InputPort2,DigitalInputBuffers

元器件交易网

PreliminaryTechnicalDataAD9779

|Page33of34

OutlineDimensions

元器件交易网

AD9779PreliminaryTechnicalData

|Page34of34

ESDCAUTION

ORDERINGGUIDE

Table15:OrderingGuide

ESD(electrostaticdischarge)ostaticchargesashighas4000Vreadilyaccumulateonthe

ghthisproductfeaturesproprietary

ESDprotectioncircuitry,permanentdamagemayoccurondevicessubjectedtohighenergyelectrostaticdischarges.

Therefore,properESDprecautionsarerecommendedtoavoidperformancedegradationorlossoffunctionality.

ModelTemperatureRangeDescription

AD9779BSV

-40°Cto+85°C(Ambient)

100-LeadTQFP,ExpodPaddle

AD9779/PCB25°C(Ambient)EvaluationBoard

©2005AnalogDevices,arksand

registeredtrademarksarethepropertyoftheirrespectiveowners.

PR05363–0–1/05(PrD)

元器件交易网